H01L2924/16251

Ceramic Encapsulating Casing and Mounting Structure Thereof
20220320023 · 2022-10-06 ·

A ceramic encapsulating casing and a mounting structure thereof are provided. The ceramic encapsulating casing includes a ceramic substrate, a ceramic insulator, a cover plate and a pad structure. The ceramic substrate is provided with a cavity with an upward opening. The ceramic insulator is disposed on the ceramic substrate and provided with a radio frequency transmission structure. The pad structure is arranged on a bottom surface of the ceramic substrate. and includes a plurality of second pads that are arranged for transmitting signals and arranged in an array manner. A plurality of solder balls are attached to the plurality of second pads in one-to-one correspondence.

HIGH-FREQUENCEY PACKAGE, HIGH-FREQUENCY MODULE, AND RADIO WAVE ABSORPTION METHOD
20230103894 · 2023-04-06 · ·

A high-frequency package includes a radio wave shielding portion that shields radio waves radiated from a high-frequency component, a radio wave absorber that is arranged facing the high-frequency component and that absorbs the radio waves, and an adjusting means that enables adjustment of distance from the radio wave absorber to the high-frequency component by adjusting a position of the radio wave absorber with respect to the radio wave shielding portion.

Semiconductor Device and Method for Manufacturing The Same
20230154822 · 2023-05-18 ·

A semiconductor device includes a first heat sink formed in contact with a back surface of a first semiconductor chip, and a second heat sink formed in contact with a back surface of a second semiconductor chip. The first heat sink is made of a material with larger thermal conductivity than that of the first semiconductor chip and has a heat dissipation surface exposed from the mold resin layer to the outside. The second heat sink is made of a material with larger thermal conductivity than that of the second semiconductor chip and has a heat dissipation surface exposed from the mold resin layer to the outside.

SYSTEM IN A PACKAGE (SIP) WITH AIR CAVITY
20230145639 · 2023-05-11 ·

A system in package (SiP) with an air cavity is disclosed. In one aspect, a technique to bond a lid over the air cavity that reduces the risk of cavity integrity failure is provided. More specifically, a metal ring is provided that conforms to or is congruent to a shape of a lower lip of the lid. A dielectric material covers the metal ring, and a low modulus epoxy is used to bind the lower lip of the lid to the dielectric material. The lid and metal ring may have comparable thermal coefficients, which, when coupled with the low modulus epoxy, reduces chance of gross failure of the cavity.

INTERPOSER STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
20230148222 · 2023-05-11 ·

An interposer structure includes: an interposer substrate; an interposer through electrode penetrating through the interposer substrate in a vertical direction; a redistribution structure on the interposer substrate and including a redistribution pattern connected to the interposer through electrode and a redistribution insulating layer on side surfaces of the redistribution pattern on the interposer substrate; a conductive post on the redistribution structure and connected to the redistribution pattern; and an interposer insulating layer on side surfaces of the conductive post on the redistribution structure.

Warpage Compensation for BGA Package

Electronic assemblies and methods of assembly are described. In an embodiment, an electronic assembly includes a stiffener structure shear bonded to an opposite side of a module substrate from a ball grid array (BGA) package. The stiffener structure may be shear bonded at elevated temperature after bonding of the BGA package to lock in a flat or near-flat surface contour of the module substrate.

Apparatuses including conductive structure layouts

Embodiments of the disclosure are drawn to arrangements of one or more “cuts” or pattern of cuts in conductive structures. Wiring layers may each include a cut pattern including a set of cuts through conductive structures of the wiring layers where each of the cuts is offset from the other in a direction orthogonal to the cut. The cut pattern in a wiring layer may be orthogonal to the cut pattern in another wiring layer. In some examples, the cut pattern may be a stair-step pattern. In some examples, the cut pattern may be interrupted by other conductive structures.

Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring

Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

STACKED SILICON PACKAGE ASSEMBLY HAVING CONFORMAL LID
20170372979 · 2017-12-28 · ·

A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes integrated circuit (IC) dies, a packaging substrate, and a lid. The packaging substrate has a die receiving area that is defined by the laterally outermost extents of the IC dies mounted to the packaging substrate. The lid a surface that includes a first region and a second region. The first region is disposed over the first IC die while the second region of the lid extends below the second surface the first IC die and is spaced above the packaging substrate. At least a portion of the second region of the lid is overlapped with the die receiving area.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method for forming a packaged electronic device includes providing a substrate having a first major surface and an opposing second major surface. The method includes attaching an electronic device to the first major surface of the substrate and providing a first conductive structure coupled to at least a first portion of the substrate. The method includes forming a dielectric layer overlying at least part of the first conductive structure. The method includes forming a conductive layer overlying the dielectric layer and connected to a second portion of the substrate. The first conductive structure, the dielectric layer, and conductive layer are configured as a capacitor structure and further configured as one or more of an enclosure structure or a stiffener structure for the packaged electronic device.