Semiconductor Device and Method for Manufacturing The Same

Abstract

A semiconductor device includes a first heat sink formed in contact with a back surface of a first semiconductor chip, and a second heat sink formed in contact with a back surface of a second semiconductor chip. The first heat sink is made of a material with larger thermal conductivity than that of the first semiconductor chip and has a heat dissipation surface exposed from the mold resin layer to the outside. The second heat sink is made of a material with larger thermal conductivity than that of the second semiconductor chip and has a heat dissipation surface exposed from the mold resin layer to the outside.

Claims

1. A semiconductor device comprising: an interconnect layer with an interconnect formed thereon; a first semiconductor chip and a second semiconductor chip disposed on the interconnect layer and molded with a mold resin layer made of a mold resin; a first integrated circuit formed on a main surface of the first semiconductor chip, the main surface facing toward the interconnect layer, the first integrated circuit being connected to the interconnect; a second integrated circuit formed on a main surface of the second semiconductor chip, the main surface facing toward the interconnect layer, the second integrated circuit being connected to the interconnect; a first heat sink formed in contact with a back surface of the first semiconductor chip and made of a material having a larger heat conductivity than that of the first semiconductor chip, the first heat sink having a heat dissipation surface exposed from the mold resin layer to an outside; and a second heat sink formed in contact with a back surface of the second semiconductor chip and made of a material having a larger heat conductivity than that of the second semiconductor chip, the second heat sink having a heat dissipation surface exposed from the mold resin layer to the outside.

2. The semiconductor device according to claim 1, wherein a total thickness of the first semiconductor chip and the first heat sink is the same as a total thickness of the second semiconductor chip and the second heat sink.

3. The semiconductor device according to claim 1, wherein a material of the first semiconductor chip is different from a material of the second semiconductor chip.

4. The semiconductor device according to claim 1, wherein the heat dissipation surface of the first heat sink and the heat dissipation surface of the second heat sink each have an uneven structure.

5. A method for producing a semiconductor device, the method comprising: a first step of fixing a first heat sink made of a material having a larger heat conductivity than that of a first semiconductor chip with a first integrated circuit formed on a main surface thereof, in contact with a back surface of the first semiconductor chip; a second step of fixing a second heat sink made of a material having a larger heat conductivity than that of a second semiconductor chip with a second integrated circuit formed on a main surface thereof, in contact with a back surface of the second semiconductor chip; a third step of fixing the first semiconductor chip with the first heat sink fixed thereto onto a support substrate, with a surface with the first integrated circuit of the first semiconductor chip facing the support substrate; a fourth step of fixing the second semiconductor chip with the second heat sink fixed thereto onto the support substrate, with a surface with the second integrated circuit of the second semiconductor chip facing the support substrate; a fifth step of molding, on the support substrate, the first semiconductor chip with the first heat sink fixed thereto and the second semiconductor chip with the second heat sink fixed thereto, using a mold resin, to form a mold resin layer; a sixth step of separating the mold resin layer from the support substrate; a seventh step of, after separating the mold resin from the support substrate, disposing the first semiconductor chip and the second semiconductor chip on an interconnect layer having an interconnect and connecting the first integrated circuit and the second integrated circuit to the interconnect such that the first semiconductor chip and the second semiconductor chip are is a state of being molded with the mold resin layer on the interconnect layer; and an eighth step of exposing a heat dissipation surface of the first heat sink and a heat dissipation surface of the second heat sink from the mold resin layer to an outside.

6. The method for producing a semiconductor device according to claim 5, wherein in the eighth step, the heat dissipation surface of the first heat sink and the heat dissipation surface of the second heat sink are exposed from the mold resin layer to the outside by grinding and polishing the mold resin layer from the heat dissipation surface side of the first heat sink and the second heat sink.

7. The semiconductor device according to claim 2, wherein a material of the first semiconductor chip is different from a material of the second semiconductor chip.

8. The semiconductor device according to claim 2, wherein the heat dissipation surface of the first heat sink and the heat dissipation surface of the second heat sink each have an uneven structure.

9. The semiconductor device according to claim 3, wherein the heat dissipation surface of the first heat sink and the heat dissipation surface of the second heat sink each have an uneven structure.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0030] FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.

[0031] FIG. 2A is a cross-sectional view showing the state of the semiconductor device in an intermediate step for illustrating a method for producing a semiconductor device according to the embodiment of the present invention.

[0032] FIG. 2B is a cross-sectional view showing the state of the semiconductor device in an intermediate step for illustrating the method for producing a semiconductor device according to the embodiment of the present invention.

[0033] FIG. 2C is a cross-sectional view showing the state of the semiconductor device in an intermediate step for illustrating the method for producing a semiconductor device according to the embodiment of the present invention.

[0034] FIG. 2D is a cross-sectional view showing the state of the semiconductor device in an intermediate step for illustrating the method for producing a semiconductor device according to the embodiment of the present invention.

[0035] FIG. 2E is a cross-sectional view showing the state of the semiconductor device in an intermediate step for illustrating the method for producing a semiconductor device according to the embodiment of the present invention.

[0036] FIG. 2F is a cross-sectional view showing the state of the semiconductor device in an intermediate step for illustrating the method for producing a semiconductor device according to the embodiment of the present invention.

[0037] FIG. 2G is a cross-sectional view showing the state of the semiconductor device in an intermediate step for illustrating the method for producing a semiconductor device according to the embodiment of the present invention.

[0038] FIG. 2H is a cross-sectional view showing the state of the semiconductor device in an intermediate step for illustrating the method for producing a semiconductor device according to the embodiment of the present invention.

[0039] FIG. 3 is a cross-sectional view showing another configuration of the semiconductor device according to the embodiment of the present invention.

[0040] FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device with a WLP structure.

[0041] FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device with a WLP structure.

DESCRIPTION OF EMBODIMENTS

[0042] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1. This semiconductor device includes an interconnect layer 101, and a first semiconductor chip 102 and a second semiconductor chip 103 that are disposed on the interconnect layer 101.

[0043] An interconnect 101a, which is made of metal, is formed on the interconnect layer 101. A first integrated circuit 102a that is electrically connected to the interconnect 101a is formed on a main surface of the first semiconductor chip 102 that faces toward the interconnect layer 101 side. A second integrated circuit 103a that is electrically connected to the interconnect 101a is formed on a main surface of the second semiconductor chip 103 that faces toward the interconnect layer 101 side. The first integrated circuit 102a is connected to the second integrated circuit 103a by the interconnect 101a. The first semiconductor chip 102 and the second semiconductor chip 103 are molded on the interconnect layer 101 by a mold resin layer 106, which is made of mold resin.

[0044] The semiconductor device also includes a first heat sink 104 that is formed in contact with a back surface of the first semiconductor chip 102, and a second heat sink 105 that is formed in contact with a back surface of the second semiconductor chip 103. The first heat sink 104 is made of a material with larger thermal conductivity than that of the first semiconductor chip 102, and has a heat dissipation surface exposed from the mold resin layer 106 to the outside. The second heat sink 105 is made of a material with larger thermal conductivity than that of the second semiconductor chip 103, and has a heat dissipation surface exposed from the mold resin layer 106 to the outside. The heat dissipation surfaces are opposite surfaces to the surfaces on the semiconductor chip side.

[0045] The first heat sink 104 and the second heat sink 105 may be made of an insulating material such as silicon carbide, aluminum nitride, beryllium oxide, or diamond, for example. The first heat sink 104 and the second heat sink 105 may also be made of metal such as aluminum, copper, or gold.

[0046] In the semiconductor device, the total thickness of the first semiconductor chip 102 and the first heat sink 104, the total thickness of the second semiconductor chip 103 and the second heat sink 105, and the thickness of the mold resin layer 106 are equal to each other. As a result, the heat dissipation surface of the first heat sink 104 and the heat dissipation surface of the second heat sink 105 are exposed from the mold resin layer 106 to the outside.

[0047] Although the first semiconductor chip 102 and the second semiconductor chip 103 have different thicknesses in the example shown in FIG. 1, the first semiconductor chip 102 and the second semiconductor chip 103 may alternatively have different thicknesses. The material of the first semiconductor chip 102 may be different from the material of the second semiconductor chip 103. The thicknesses of the first heat sink 104 and the second heat sink 105 may be set as appropriate.

[0048] In the semiconductor device, a terminal 101b is formed under the interconnect layer 101, and the interconnect layer 101 is electrically connected (mounted) to a printed board 107 via the terminal 101b. This example describes a face-down process for WLP and secondary mounting on the printed board 107. However, the effect of the present invention can also be obtained for other processes such as a face-up process for WLP and designs without secondary mounting.

[0049] With the semiconductor device according to the above-described embodiment, first, the first semiconductor chip 102 is thermally and electrically separated from the second semiconductor chip 103 by the mold resin layer 106 in the surface direction of the interconnect layer 101. Further, the first heat sink 104 connected to the first semiconductor chip 102 is thermally and electrically separated from the second heat sink 105 connected to the second semiconductor chip 103 by the mold resin layer 106. For this reason, the first semiconductor chip 102 is thermally separated from the second semiconductor chip 103. No matter what the conductivity of the body of each semiconductor chip is, the potentials of the surfaces on which the integrated circuits are formed do not become equal.

[0050] In addition, with the semiconductor device according to the embodiment, heat of the first semiconductor chip 102 is dissipated from a heat dissipation surface capable of coming into contact with outside air, via the first heat sink 104 that is directly connected to the first semiconductor chip 102. Similarly, heat of the second semiconductor chip 103 is dissipated from a heat dissipation surface capable of coming into contact with outside air, via the second heat sink 105 that is directly connected to the second semiconductor chip 103. As a result, heat dissipation deriving from the mold resin layer 106 is improved.

[0051] As a result, with the semiconductor device according to the embodiment, it is possible to suppress thermal and electrical crosstalk while improving heat dissipation.

[0052] Next, a method for producing a semiconductor device according to the present invention will be described with reference to FIGS. 2A to 2H.

[0053] First, as shown as (a) in FIGS. 2A to 2C, the first heat sink 104 that is made of a material with larger thermal conductivity than that of the first semiconductor chip 102 is fixed in contact with the back surface of the first semiconductor chip 102 with the first integrated circuit 102a formed on its main surface (first step). Also, as shown as (b) in FIGS. 2A to 2C, the second heat sink 105 that is made of a material with larger thermal conductivity than that of the second semiconductor chip 103 is fixed in contact with the back surface of the second semiconductor chip 103 with the second integrated circuit 103a formed on its main surface (second step).

[0054] For example, the above steps can be carried out by bonding a first heat sink wafer to serve as the first heat sink 104 to a first wafer to form the first semiconductor chip 102, and bonding a second heat sink wafer to serve as the second heat sink 105 to a second wafer to form the second semiconductor chip 103. A known semiconductor wafer bonding technique (e.g., surface activated bonding) can be used in the above bonding. Next, the first and second wafers are thinned and polished so that the thickness of the first wafer with the first heat sink wafer bonded thereto is equal to the thickness of the second wafer with the second heat sink wafer bonded thereto.

[0055] Next, semiconductor layers are formed on the first and second wafers by means of a known crystal growth technique. A desired functional circuit is also formed by implementing a known semiconductor process to these semiconductor layers. A plurality of first integrated circuits 102a are formed on the first wafer, and a plurality of second integrated circuits 103a are formed on the second wafer (FIG. 2B). Thereafter, the first heat sink 104 is fixed to the back surface of the first semiconductor chip 102 with the first integrated circuits 102a formed on the main surface thereof, as shown as (a) in FIG. 2C, by dicing the wafers, for example. Also, the second heat sink 105 is fixed to the back surface of the second semiconductor chip 103 with the second integrated circuits 103a formed on the main surface thereof, as shown as (b) in FIG. 2C.

[0056] Next, the surface of the first semiconductor chip 102 cut out into a chip on which a first integrated circuit 102a is formed is attached and fixed to an adhesive layer 122 fixed onto a support substrate 121, as shown in FIG. 2D. Further, the surface of the second semiconductor chip 103 cut out into a chip on which a second integrated circuit 103a is formed is attached and fixed to the adhesive layer 122 (third and fourth steps). Although the figures show one pair of the first semiconductor chip 102 and the second semiconductor chip 103, more than one pairs can be simultaneously fixed (mounted) onto the support substrate 121, for example.

[0057] The support substrate 121 need only have a size corresponding to the semiconductor production apparatus used when the later-described interconnect layer 101 is formed. The material of the support substrate 121 can be semiconductor such as silicon, glass, resin, or metal, for example. The adhesive 122 can be made of a material capable of withstanding the temperature at which the later-described mold resin layer 106 is formed.

[0058] Next, the first semiconductor chip 102 to which the first heat sink 104 is fixed and the second semiconductor chip 103 to which the second heat sink 105 is fixed are molded with mold resin on the support substrate 121 to form the mold resin layer 106, as shown in FIG. 2E (fifth step). The mold resin layer 106 can be formed by forming a layer of the mold resin and curing the formed layer of the mold resin by means of a known compression mold method or transfer mold method, for example.

[0059] Next, the mold resin layer 106 is separated from the support substrate 121 (sixth step), and the surface on which the integrated circuits are formed is exposed, as shown in FIG. 2F. For example, the mold resin layer 106 can be separated from the support substrate 121 by peeling the adhesive layer 122. For example, a method that does not degrade characteristics of the integrated circuits such as a laser peeling method, a thermal peeling method, a mechanical peeling method, or a solvent peeling method can be selected.

[0060] Next, after the mold resin is separated from the support substrate 121, the first semiconductor chip 102 and the second semiconductor chip 103 are formed on the interconnect layer 101 including the interconnect 101a, as shown in FIG. 2G. The first integrated circuit 102a and the second integrated circuit 103a are connected to the interconnect 101a. Further, a state is entered where the first semiconductor chip 102 and the second semiconductor chip 103 are molded with the mold resin layer 106 on the interconnect layer 101 (seventh step).

[0061] For example, the interconnect layer 101 can be formed on the first semiconductor 102 and the second semiconductor chip 103 that are molded with the mold resin layer 106, by means of the build-up method. For example, after the first semiconductor chip 102 and the second semiconductor chip 103 are molded with the mold resin layer 106, the interconnect layer 101 can be obtained by forming a metal layer on the mold resin layer 106 by means of evaporation or plating, for example, and patterning the metal layer to form the interconnect 101a. Further, the terminal 101b to be connected to the interconnect 101a is formed on the interconnect layer 101 by means of solder bumps or the like, for example. Although the figures show one pair of the first semiconductor chip 102 and the second semiconductor chip 103, more than one pairs can be simultaneously molded with the mold resin layer 106, for example.

[0062] Next, the heat dissipation surface of the first heat sink 104 and the heat dissipation surface of the second heat sink 105 are exposed from the mold resin layer 106 to the outside, as shown in FIG. 2H (eighth step). For example, the heat dissipation surface of the first heat sink 104 and the heat dissipation surface of the second heat sink 105 are exposed by mechanically polishing (grinding and polishing), with a grinder or the like, the surface of the interconnect layer 101 on the side where the heat sinks are deposed. Thereafter, pairs of the first semiconductor chip 102 and the second semiconductor chip 103 are separated into individual pieces using a dicing device. Thereafter, the semiconductor device shown in FIG. 1 is obtained by mounting a package of the separated piece of a pair of the first semiconductor chip 102 and the second semiconductor chip 103 on the printed board 107 via the terminal 101b. If, for example, solder bumps are used, the mounting can be realized using known reflow technology.

[0063] According to the above-described embodiment, first, the first semiconductor chip 102 is separated from the second semiconductor chip 103 by the mold resin layer 106. Thus, thermal and electrical crosstalk between the first heat sink 104 and the second heat sink 105 is suppressed.

[0064] In addition, heat generated from the first integrated circuit 102a and the second integrated circuit 103a of the first semiconductor chip 102 and the second semiconductor chip 103 is transferred from the bodies of the semiconductor chips to the first heat sink 104 and the second heat sink 105 that have higher heat conductivity, and is then dissipated to the atmosphere. Thus, according to the embodiment, heat dissipation can be improved since the mold resin layer 106 having significantly low heat conductivity is not present in the heat dissipation path.

[0065] In addition, the first heat sink 104 and the second heat sink 105 ensure the mechanical strength of the semiconductor device according to the present embodiment. Therefore, the semiconductor portions of the semiconductor chips that have low thermal conductivity can be extremely thinned without breaking the device due to lack of mechanical strength during the production process, thus making it possible to improve heat dissipation efficiency.

[0066] In the method for producing a semiconductor device according to the present embodiment, dicing can be performed after bonding heat sinks of the same size to a semiconductor wafer. As a result, semiconductor chips equipped with the heat sinks in advance can be made into WLPs, and the mounting process can be shortened in terms of time without having to install a heat sink to each package. The advantage of the method for producing a WLP is that WLPs can be produced in bulk at the wafer level. However, when a heat sink is attached, it was conventionally necessary to attach it to each package, and the heat sink attachment process led to an increase in the time required for the mounting process. In contrast, the above-described embodiment makes it possible to both suppress thermal and electrical crosstalk and shorten the time required for the mounting process, while improving heat dissipation.

[0067] When it is attempted to expose the backside of each semiconductor chip in a WLP in which two semiconductor chips including different semiconductors are encapsulated, the mold resin and the semiconductor chips are scraped. In this case, it is necessary to give consideration to physical property values of the mold resin and the semiconductor chips in regard to grinding conditions. For example, the mold resin and two types of semiconductor chips of dissimilar materials must be conditioned for grinding for each combination of semiconductor chips. In contrast, according to the embodiment, the grinding conditions are determined for the combination of the mold resin and a specific type of heat sink. Therefore, the grinding conditions do not depend on the semiconductor chips, which has the advantage of making it easier to set grinding conditions.

[0068] A configuration with an uneven structure formed on the heat dissipation surface of the first heat sink 104a and the heat dissipation surface of the second heat sink 105a as shown in FIG. 3 may alternatively be employed. For example, an uneven structure can be formed on the heat dissipation surface of the first heat sink 104a and the heat dissipation surface of the second heat sink 105a by partially etching these surfaces. The surface area of each heat dissipation surface can be increased by thus forming the uneven structure, thus making it possible to further improve heat dissipation efficiency.

[0069] As described above, according to the present invention, a heat sink with a heat dissipation surface exposed from the mold resin layer to the outside is provided in contact with the back surface of each semiconductor chip. It is, therefore, possible to suppress thermal and electrical crosstalk while improving heat dissipation.

[0070] Note that the present invention is not limited to the above-described embodiment, and it is apparent that many modifications and combinations can be carried out by those with common knowledge in this field within the technical idea of the present invention.

REFERENCE SIGNS LIST

[0071] 101 Interconnect layer [0072] 101a Interconnect [0073] 101b Terminal [0074] 102 First semiconductor chip [0075] 102a First integrated circuit [0076] 103 Second semiconductor chip [0077] 103a Second integrated circuit [0078] 104 First heat sink [0079] 105 Second heat sink [0080] 106 Mold resin layer [0081] 107 Printed board