An operational amplifier includes a first output transistor and a second output transistor connected in series between two power nodes, the second output transistor having a semiconductor type opposite to the first output transistor, the first output transistor and the second output transistor being electrically coupled at an output node, and gates of the first output transistor and the second output transistor being connected to a first drive node and a second drive node respectively; and a decoupling capacitor circuit electrically connected between the first drive node and the second drive node.

This disclosure relates to an output buffer including an input stage configured to monitor a difference between an input voltage and an output voltage, a current summing stage configured to generate amplified currents and control voltages according to the difference between the input voltage and the output voltage monitored by the input stage, an output stage configured to perform a pull-up operation or a pull-down operation according to the control voltages output from the current summing stage to generate the output voltage at an output terminal, and a slew boost circuit configured to perform a slew boost operation of adjusting some currents among currents provided from the current summing stage to the input stage according to the difference between the input voltage and the output voltage by monitoring the difference between the input voltage and the output voltage and selectively perform the slew boost operation by monitoring the control voltages.

Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.

An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and a first analog residue signal corresponding to a difference between the first digital value and the analog input signal. An inverter based residue amplifier is configured to receive the first analog residue signal, amplify the first analog residue signal, and output an amplified residue signal. The amplified residue signal is converted to a second digital value, and the first and second digital values are combined to create a digital output signal corresponding to the analog input voltage signal.

An active load stage converts a first input current and a second input current into a first voltage and a second voltage. A driver amplifier operates upon receiving the first voltage and the second voltage from the active load stage, and outputs a current to an output terminal. The driver amplifier has a first transistor and a second transistor connected in series between a first reference potential terminal and a second reference potential terminal. The first transistor receives the first voltage at a gate and passes a first current, and the second transistor receives the second voltage at a gate and passes a second current. A minimum selector provides feedback to the first voltage and the second voltage such that an absolute value of each of the first current and the second current becomes more than or equal to a quiescent current of the driver amplifier.

An amplifier comprising a main branch amplifier and an auxiliary branch amplifier, wherein one branch is a constant current-biased branch, and another branch is a voltage biased branch, with the branches connected in cascode configuration to form a load modulated amplifier.

Disclosed is a power amplifier system having a main amplifier with an input coupled to a main radio frequency (RF) input and an output connected to a main RF output, wherein the main amplifier exhibits a nonlinear gain characteristic with compression. At least one compression compensating amplifier has a signal input coupled to the common RF input and a signal output coupled to the common RF output.

A local oscillator buffer circuit comprises a complementary common-source stage comprising a first p-channel transistor (MCSP) and a first n-channel transistor (MCSN), arranged such that their respective gate terminals are connected together at a first input node, and their respective drain terminals of each of is connected together at a buffer output node. A complementary source-follower stage comprises a second p-channel transistor (MSFP) and a second n-channel transistor (MSFN), arranged such that their respective gate terminals are connected together at a second input node, and their respective source terminals are connected together at the buffer output node.

An active load stage converts a first input current and a second input current into a first voltage and a second voltage. A driver amplifier operates upon receiving the first voltage and the second voltage from the active load stage, and outputs a current to an output terminal. The driver amplifier has a first transistor and a second transistor connected in series between a first reference potential terminal and a second reference potential terminal. The first transistor receives the first voltage at a gate and passes a first current, and the second transistor receives the second voltage at a gate and passes a second current. A minimum selector provides feedback to the first voltage and the second voltage such that an absolute value of each of the first current and the second current becomes more than or equal to a quiescent current of the driver amplifier.

An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and a first analog residue signal corresponding to a difference between the first digital value and the analog input signal. An inverter based residue amplifier is configured to receive the first analog residue signal, amplify the first analog residue signal, and output an amplified residue signal. The amplified residue signal is converted to a second digital value, and the first and second digital values are combined to create a digital output signal corresponding to the analog input voltage signal.