In accordance with an embodiment, a method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor includes: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.

In some embodiments, a compensated power detector can include a power detector that includes a first detection cell having a bias input and an output, and a second detection cell having a signal input, a bias input and an output. The power detector can further include an error amplifier having a first input coupled to the output of the first detection cell, and a second input for receiving a reference voltage. The error amplifier can be configured to provide an output voltage to each of the bias inputs of the first and second detection cells, such that an output of the second detection cell is representative of power of a radio-frequency signal received at the signal input with an adjustment for one or more non-signal effects as measured by the first detection cell and the error amplifier.

A switched emitter follower circuit is constituted by a transistor in which a base is connected to a signal input terminal, a power voltage is applied to a collector, and an emitter is connected to a signal output terminal, a capacitor in which one end is connected to the collector of the transistor, and the other end is connected to the emitter of the transistor, and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the transistor, a negative-phase clock output terminal is connected to the base of the transistor, and a multiplication result of a differential clock signal and a differential clock signal input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal.

Provided herein are amplifiers, such as buffers, with increased headroom. An amplifier stage includes a follower transistor and current source configured to receive a power supply voltage comprising an alternating current component and a direct current component. The alternating current component of the power supply voltage has substantially the same frequency and magnitude as the input signal received by the follower transistor. In radio frequency (RF) and intermediate frequency (IF) buffer applications, for example, the increased headroom can allow for linear buffering of an input signals with increased amplitude so that the output power one decibel (OP1dB) compression point can be increased.

In at least one embodiment, a differential amplifier including first and second current transfer systems, a current difference producing system, and a feedback network circuit is provided. The first current transfer system generates a first differential current signal. The second current transfer system generates a second differential current signal. The current difference producing system receives the first differential current signal and the second differential current signal and generates a voltage difference signal that is indicative of a difference between a first current signal and a second current signal. The feedback network circuit converts the voltage difference signal into at least two converted current signals and provides the at least two converted current signals to one of the first and second current transfer systems or the current difference producing system to minimize the difference between the first current signal and the second current signal.

According to the present invention, an integrated circuit includes a first amplifier stage, a second amplifier stage, a first signal line connecting an output of the first amplifier stage and an input of the second amplifier stage to each other, a first plane for ground connected to the first amplifier stage, a second plane for ground connected to the second amplifier stage and at least one at least one line for ground connecting the first plane and the second plane to each other, wherein the at least one line has a center line having a length of 10 μm to 1 mm, a width of the at least one line is ⅓ or less of a width of the first plane, and a pattern ratio is 1 or more.

A variable gain amplifier and an electronic apparatus. The variable gain amplifier includes a first transconductance stage circuit and a second transconductance stage circuit, where the first transconductance stage circuit includes a first amplifying circuit and a second amplifying circuit, the second transconductance stage circuit includes a third amplifying circuit and a fourth amplifying circuit, the first amplifying circuit and the fourth amplifying circuit form a differential input pair, and the second amplifying circuit and the third amplifying circuit form a differential input pair, and where each amplifying circuit of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit includes a plurality of parallel transistors, and bias control of the plurality of transistors is independent of each other.

A temperature detector is used to detect a temperature of a circuit under test, and includes a temperature coefficient component, a multiplier, an impedance component and a node. The temperature coefficient component is arranged in proximity to the circuit under test. A control terminal of the multiplier is coupled to a second terminal of the temperature coefficient component. The impedance component is coupled between the second terminal of the temperature coefficient component and the control terminal of the multiplier, or between a second terminal of the multiplier and a third voltage terminal. The node is formed between the second terminal of the temperature coefficient component and the control terminal of the multiplier. A voltage at the node and an amplified detection current flowing to a first terminal of the multiplier are positively correlated to the temperature of the circuit under test.

In some embodiments, a compensated power detector can include a power detector that includes a first detection cell having a bias input and an output, and a second detection cell having a signal input, a bias input and an output. The power detector can further include an error amplifier having a first input coupled to the output of the first detection cell, and a second input for receiving a reference voltage. The error amplifier can be configured to provide an output voltage to each of the bias inputs of the first and second detection cells, such that an output of the second detection cell is representative of power of a radio-frequency signal received at the signal input with an adjustment for one or more non-signal effects as measured by the first detection cell and the error amplifier.

For broadband data communication, a data signal voltage at a signal input node can be converted to an output signal current at a signal output node. A first transistor device can contribute to the output signal current, with its transconductance or other gain reduced to accommodate larger signal swings, at which a second transistor can turn on and increase an effective resistance value of at least a portion of a gain degeneration resistor associated with the first transistor device. The second transistor can also contribute to the output signal current to help maintain or enhance an overall gain between the signal input node and the signal output node. Multiple secondary stages, push-pull arrangements, buffer amplifier configurations (which may or may not contribute to current in the gain degeneration resistor), input and output transformers, negative feedback to help reduce component variability, and frequency modification circuits or components are also described.