A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive in an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate including a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.

A method includes: selectively generating a first current by a first current generating circuit according to a first control signal; generating a second current by a second current generating circuit; and comparing a first input signal and a second input signal at a common node to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.

A comparator is disclosed, for comparing a first input voltage (e+) with a second input voltage (e−) and generating a corresponding output voltage (out). The comparator comprises: a first input terminal (e+) for receiving the first input voltage: a second input terminal (e−) for receiving the second input voltage; an output terminal (out) for outputting the output voltage; a first supply rail (VCC) for providing a first supply voltage; and a second supply rail (VDD) for providing a second supply voltage. The comparator further comprises: a follower stage comprising a first follower stage supply terminal coupled to the first supply rail, a second follower stage supply terminal coupled to the second supply rail, a follower stage input terminal coupled to the second input terminal, and a follower stage output terminal for providing a follower stage output voltage; and an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal coupled to the first input terminal, and an inverter stage output terminal for providing an inverter stage output voltage and coupled to the output terminal.

A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

Various implementations are presented herein that improve the performance of dynamic quantizers over process, voltage and temperature (“PVT”) and input common mode (Vcm) variations. This can be accomplished by separating and then varying the voltage supply to the reset devices connected to the input devices of the quantizer while leaving the supply to the other parts of the quantizer unchanged. The timing performance of the quantizer can be improved (reduced clock-to-q) by lowering the voltage supply to the reset devices. The input referred RMS noise and offset voltage of the circuit can be improved (reduced) by raising the voltage supply to the reset devices. Similarly, increases in Vcm due to process and voltage scaling can be mitigated by raising the voltage supply to the reset devices. Control systems are also provided herein to control the voltage supply to the reset devices to accomplish these and other objectives.

Disclosed is a dual clock signal to pulse-width modulated signal conversion circuit, comprising: a first counter, an input end of which inputs a first clock signal, and an output end of which outputs a divided signal; an edge reset circuit, an input end of which inputs the divided signal, the output end of which outputs a first reset pulse signal and a second reset pulse signal, the first reset pulse signal being configured for resetting a second counter, and the second reset pulse signal being configured for resetting a third counter; a second counter, an input end of which inputs the second clock signal and the first reset pulse signal, and an output end of which outputs the first pulse-width modulated signal; a third counter, an input end of which inputs the second clock signal and the second reset pulse signal, and an output end of which outputs the second pulse-width modulated signal; a logic processing circuit, an input end of which inputs the first pulse-width modulated signal and the second pulse-width modulated signal, and an output end of which outputs a pulse-width modulated signal PWM_OUT. The disclosure offers high precision, system stability, and good anti-interference.

Provided is a comparison circuit to which a negative voltage to be compared can be input directly. The comparison circuit includes a first input terminal, a second input terminal, a first output terminal, and a differential pair. The comparison circuit compares a negative voltage and a negative reference voltage and outputs a first output voltage from the first output terminal in response to the comparison result. The negative voltage is input to the first input terminal. A positive reference voltage is input to the second input terminal. The positive reference voltage is determined so that comparison is performed. The differential pair includes a first n-channel transistor and a second n-channel transistor each having a gate and a backgate. The first input terminal is electrically connected to the backgate of the first n-channel transistor. The second input terminal is electrically connected to the gate of the second n-channel transistor.

A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal.

Apparatuses and methods for image sensors with increased analog to digital conversion range are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to a ramp voltage input of the comparator, increasing, by a ramp generator, an auto-zero voltage level of a ramp voltage provided to the ramp voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to a bitline input of the comparator.