Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

A semiconductor device includes: a first field-effect transistor configured to have a source connected to a reference potential node; a second field-effect transistor configured to have a source connected to a drain of the first field-effect transistor, and a gate connected to the source of the first field-effect transistor; a gate signal node configured to input a gate signal therein; a first resistor configured to be connected between the gate signal node and a gate of the first field-effect transistor; and a first capacitor and a switch circuit configured to be connected between a drain of the second field-effect transistor and the gate of the first field-effect transistor, in which the switch circuit is connected in series with the first capacitor.

An off chip driver circuit includes a first power rail, a second power rail, an input/output pad, a pull-up circuit, a pull-down circuit. The pull-up circuit is configured to selectively activate at least one of charging paths between the first power rail and the input/output pad. The pull-up circuit includes a first resistor and PMOS transistors arranged on the charging paths, and the first resistor is coupled between the first power rail and the PMOS transistors. The pull-down circuit is configured to selectively activate at least one of discharging paths between the second power rail and the input/output pad. The pull-down circuit includes a second resistor and NMOS transistors arranged on the discharging paths, and the second resistor is coupled between the second power rail and the NMOS transistors.

A radio frequency (RF) switch includes a switchable RF path including a plurality of transistors coupled in series; a gate bias network including a plurality of resistors, wherein the gate bias network is coupled to each of the plurality of transistors in the switchable RF path; and a bypass network including a first plurality of transistors coupled in parallel to each of the plurality of transistors in the switchable RF path and a second plurality of transistors coupled in parallel to each of the plurality of resistors in the gate bias network.

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

A method for operating an electrical circuit including at least one half-bridge formed from two transistors wherein the electrical circuit is switched over between a first switching state, in which the first transistor of the half-bridge is switched to conductive by a first voltage value of a first control voltage and the second transistor of the half-bridge is switched to blocking by a second voltage value of a second control voltage, and a second switching state, in which the first transistor is switched to blocking by a second voltage value of the first control voltage and the second transistor is switched to conductive by a first voltage value of the second control voltage, wherein a dead time state, in which both transistors are switched to blocking, is assumed chronologically between the first switching state and the second switching state.

Boot-strapping systems and techniques for circuits are described. One or more solid-state switches of a switched regulation circuit may be implemented using core transistors and the boot-strapping systems, rather than I/O transistors.

A power electronic module (2) includes at least one semiconductor switch (4) and a gate-source control unit. The gate-source control unit includes an asymmetric transient voltage suppressor (TVS) diode (8) or two Zener diodes (10, 10) or one or more avalanche diodes arranged between the gate terminal (G) and the source terminal (S) of the semiconductor switch (4).

An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switche to the feedback switches to accelerate the pull up or the pull down.

Disclosed a drive method, a drive circuit for a power switch and a power supply system. During the turning-on period of the power switch, which can be roughly divided into three processes, a current limiting module is used to limit the current flowing through the power switch for preventing current overshoot, a logic control module is used for controlling the current limiting module not to operate before the turning-on period and the control terminal of the power switch is turned off; during the turning-on period, a feedback circuit adjusts the gate voltage of the power switch for controlling the current flowing through the power switch to reach a predetermined limited value quickly and then maintain at the limited value until the power switch is fully turned on. The current limiting module can be employed in various embodiments. According to the disclosure, the current flowing through the power switch can be effectively controlled during the turning-on period, and the driving time for turning on the power switch is decreased.