A method for operating an electrical circuit including at least one half-bridge formed from two transistors wherein the electrical circuit is switched over between a first switching state, in which the first transistor of the half-bridge is switched to conductive by a first voltage value of a first control voltage and the second transistor of the half-bridge is switched to blocking by a second voltage value of a second control voltage, and a second switching state, in which the first transistor is switched to blocking by a second voltage value of the first control voltage and the second transistor is switched to conductive by a first voltage value of the second control voltage, wherein a dead time state, in which both transistors are switched to blocking, is assumed chronologically between the first switching state and the second switching state.

According to one aspect, embodiments herein provide a power switching circuit, comprising a first terminal, a second terminal, a third terminal, and a plurality of switching devices, each switching device having a first transistor having a first gate, a first source, and a first drain, a second transistor having a second gate, a second source, a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source, and a unipolar diode configured to prevent a transition voltage applied across the first gate and the first source from exceeding a degradation threshold of the first transistor during a transition period, wherein a first switching device of the plurality of switching devices is coupled between the first and third terminals and the and a second switching device of the plurality of switching devices is coupled between the second and third terminals.

Boot-strapping systems and techniques for circuits are described. One or more solid-state switches of a switched regulation circuit may be implemented using core transistors and the boot-strapping systems, rather than I/O transistors.

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a trickle current state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

In a PIN diode drive circuit, a forward voltage is applied to a PIN diode through a first switching element and a reverse voltage is applied to the PIN diode through a second switching element. A limiting unit limits an increase rate of an absolute value of a reverse recovery current to a value smaller than a threshold value, the reverse recovery current flowing through the PIN diode when a voltage applied to the PIN diode changes from a forward voltage to a reverse voltage. The threshold value is less than 1 time and 0.5 times or more of a maximum value of the increase rate when a second peak appears regarding the reverse recovery current.

Embodiments described herein include radio frequency (RF) switches. In general, the embodiments described herein selectively bias the output terminals of one or more switching transistors in the RF switch. Such coupling can provide a bias that significantly reduces the effects of gate-lag. In one embodiment, the RF switch includes an antenna node, a first input/output (I/O) node, a second I/O node, a field-effect transistor (FET), a FET stack, and a bias coupling circuit. In this embodiment the bias coupling circuit electrically couples a gate terminal of the FET to one or more FET output terminals of the FET stack to provide a bias voltage to the output terminal(s).

In a PIN diode drive circuit, a forward voltage is applied to a PIN diode through a first switching element and a reverse voltage is applied to the PIN diode through a second switching element. A limiting unit limits an increase rate of an absolute value of a reverse recovery current to a value smaller than a threshold value, the reverse recovery current flowing through the PIN diode when a voltage applied to the PIN diode changes from a forward voltage to a reverse voltage. The threshold value is less than 1 time and 0.5 times or more of a maximum value of the increase rate when a second peak appears regarding the reverse recovery current.

Provided is a switching device including: a cascode switch including at least two transistors connected in series and receiving a switching control signal; and a third switch receiving the switching control signal, wherein the at least two transistors include a first transistor receiving the switching control signal through a control terminal and a second transistor having a control terminal connected to a first voltage source, and wherein the third switch is connected between the control terminal and the first terminal of the second transistor, is turned off when the first transistor is turned on, and is turned on when the first transistor is turned off.

A drive circuit is connected to a gate terminal of an FET connected to a DC power supply to be transformed and controlled to be turned on or off, and applies a voltage to the gate terminal to turn on the FET, the FET including a drain terminal to which a current is input, a source terminal that outputs the current input from the drain terminal, and the gate terminal that controls the current flowing from the drain terminal to the source terminal. A reverse bias circuit includes a capacitor connected to the source terminal of the FET, and a coil having one end connected between the drive circuit and the gate terminal and the other end connected between the capacitor and the source terminal.

The disclosure relates to a lighting device for frequency-modulated emission. The object to provide a lighting device comprising a light-emitting diode (LED) that allows for higher operating frequencies and that in particular has an improved quality of the emitted light signal is solved in that the lighting device comprises: an LED; a resonant driver circuit with a tuned circuit; wherein the resonant driver circuit is configured to drive the tuned circuit with an operating frequency, and wherein the tuned circuit comprises the LED. The disclosure further relates to a method of operating a lighting device and a use of a lighting device.