Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a trickle current state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

At least one aspect of the disclosure is directed to an AC switching system. The AC switching system includes a first I/O, a second I/O, a first segment including a first plurality of switches, the first segment being coupled to the first I/O, a second segment including a second plurality of switches, the second segment being coupled with the first segment and coupled to the second I/O, a third segment including a diode, the third segment being coupled to the first I/O and coupled to a junction of the first segment and the second segment, and a fourth segment including a diode, the fourth segment being coupled to the second I/O and coupled to the junction of the first segment and the second segment.

A low inductance electrical switching circuit arrangement, includes a two sided substrate with a plurality of through-substrate electrical vias. A capacitor is arranged on the substrate first side above a first via, and an electrical sink is arranged on the first side above a second via. A switching component configured to produce a plurality of current pulses is arranged on the substrate second side below the first and second via.

A surface mountable laser driver circuit package is configured to mount on a host printed circuit board (PCB). A surface mount circuit package includes a lead-frame. A plurality of laser driver circuit components is mounted on and in electrical communication with the lead-frame of the surface mount circuit package. A dielectric layer is located between the lead-frame and the host PCB and includes portals through the dielectric layer each arranged to accommodate an electrical connection between the lead-frame and the host PCB. The lead-frame and the dielectric layer are arranged such that a first lead-frame portion and a first dielectric layer portal align with a first end of a host PCB trace configured to provide a current return path for the surface mount laser driver, and a second lead-frame portion and a second dielectric layer portal align with a second end of the host PCB trace.

A fast shut-off solenoid circuit network includes a solenoid circuit and a current dissipation circuit. The solenoid circuit is operable in response to an electrical current, and configured to operate in an enable mode and a disable mode. The current dissipation circuit is configured to dissipate the current discharged from the solenoid circuit in response to invoking the disable mode. The fast shut-off solenoid circuit network further includes a dissipation bypass circuit. The dissipation bypass circuit is configured to divert the current discharged by the solenoid circuit away from current dissipation circuit when operating in the enable mode.

A FET driving circuit includes: inputs into which a DC voltage is inputted; outputs connected to gate and source electrodes of a FET; a switch; a capacitance connected across the switch; and an LC resonance circuit connected in series with the switch across the inputs. A voltage generated across the switch during switching is outputted to drive the FET. The LC resonance circuit has a first connector connected to one input and a second connector connected to the switch, and is configured with a path including an inductance and a path including an inductance and a capacitance. An impedance between the first and second connectors has two resonant frequencies. The impedance has a local maximum at the lower resonant frequency, which is higher than a switching frequency, and a local minimum at the higher resonant frequency, which is around double the switching frequency.

An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switches to the feedback switches to accelerate the pull up or the pull down.

Systems and methods are provided for improved linearity of audio amplifiers. In one example, a system includes a first current source configured to provide a first current signal having a first current source output capacitance, and a second current source configured to provide a second current signal having a second current source output capacitance, where the first and second current source output capacitances are a different value. The system further includes a first capacitor compensation device coupled to an output of the first current source configured to provide a capacitance value to compensate for the second current source output capacitance, and a second capacitor compensation device coupled to an output of the second current source configured to provide a capacitance value to compensate for the first current source output capacitance. The system further includes a plurality of switches configured to switch the first and second current signals.

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a trickle current state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

A drive circuit is connected to a gate terminal of an FET connected to a DC power supply to be transformed and controlled to be turned on or off, and applies a voltage to the gate terminal to turn on the FET, the FET including a drain terminal to which a current is input, a source terminal that outputs the current input from the drain terminal, and the gate terminal that controls the current flowing from the drain terminal to the source terminal. A reverse bias circuit includes a capacitor connected to the source terminal of the FET, and a coil having one end connected between the drive circuit and the gate terminal and the other end connected between the capacitor and the source terminal.