Transient stabilized SOI FETs

Abstract

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a trickle current state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

Claims

1. An integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate, including at least one metal-oxide-semiconductor field effect transistor (FET) having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source, and a circuit connected in series with the signal path and selectively configured such that, when the FET is in a standby mode, the circuit maintains a very low current flow through the signal path of the FET that keeps both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET close to respective active mode operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic, thereby reducing changes in accumulated charge.

2. A circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the circuit including: (a) at least one metal-oxide-semiconductor field effect transistor (FET) having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source; and (b) a switch coupled in series with the signal path of the FET, configured to selectively couple the signal path to a normal current flow path or to a trickle current path; wherein, in an active mode, the switch couples the signal path of the FET to the normal current flow path; and wherein, in a standby mode, the switch couples the signal path of the FET to the trickle current path such that both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET are close to respective active mode operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic, thereby reducing changes in accumulated charge.

3. The invention of claim 2, wherein the trickle current path has a high resistance relative to the normal current flow path.

4. A circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the circuit including: (a) at least one metal-oxide-semiconductor field effect transistor (FET) having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source; and (b) a switch coupled in series with the signal path of the FET, configured to selectively couple the signal path to a load resistance or to a high resistance; wherein, in an active mode, the switch couples the signal path of the FET to the load resistance; and wherein, in a standby mode, the switch couples the signal path of the FET to the high resistance, such that both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET are close to respective active mode operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic, thereby reducing changes in accumulated charge.

5. The invention of claim 4, wherein the high resistance is at least about 100 times greater than the load resistance.

6. An integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate, including: (a) at least one metal-oxide-semiconductor field effect transistor (FET) having a V.sub.DS characteristic and a V.sub.GS characteristic; and (b) at least one switch coupled in series with the FET and configured to be set to a standby mode in which no significant current flows through the at least one FET while maintaining essentially the same V.sub.DS characteristic and V.sub.GS characteristic for the at least one FET as during an active mode, thereby eliminating or reducing changes in accumulated charge.

7. The invention of claim 1, 2, 4, or 6, wherein the SOI substrate includes a trap rich layer susceptible to accumulated charge in or near such trap rich layer.

8. The invention of claim 1, 2, 4, or 6, further including at least one substrate contact near at least one FET.

9. The invention of claim 1, 2, 4, or 6, further including at least a partial ring of substrate contacts around at least one FET.

10. A method for eliminating or reducing changes in accumulated charge in an integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate, including: (a) providing at least one metal-oxide-semiconductor field effect transistor (FET) having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source; (b) coupling a circuit in series with the signal path, the circuit having at least a standby mode and an active mode; and (c) configuring the circuit such that, in the standby mode, the at least one FET is switched into a very low current state with respect to current flow through the signal path that keeps both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET close to respective operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic when the circuit is in the active mode, thereby reducing changes in accumulated charge.

11. A method for eliminating or reducing changes in accumulated charge in a circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, including: (a) providing at least one metal-oxide-semiconductor field effect transistor (FET) having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source; (b) coupling a switch in series with the signal path of the FET and configuring the switch to selectively couple the signal path to a normal current flow path or to a trickle current path; (c) in an active mode, setting the switch to couple the signal path of the FET to the normal current flow path; and (d) in a standby mode, setting the switch to couple the signal path of the FET to the trickle current path such that both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET are close to respective active mode operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic, thereby reducing changes in accumulated charge.

12. The method of claim 11, wherein the trickle current path has a high resistance relative to the normal current flow path.

13. A method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, including: (a) providing at least one metal-oxide-semiconductor field effect transistor (FET) having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source; (b) coupling a switch in series with the signal path of the FET, configured to selectively couple the signal path to a load resistance or to a high resistance; (c) in an active mode, setting the switch to couple the signal path of the FET to the load resistance; and (d) in a standby mode, setting the switch to couple the signal path of the FET to the high resistance, such that both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET are close to respective active mode operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic, thereby reducing changes in accumulated charge.

14. The method of claim 13, wherein the high resistance is at least about 100 times greater than the load resistance.

15. A method for eliminating or reducing changes in accumulated charge in an integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate, including: (a) providing at least one metal-oxide-semiconductor field effect transistor (FET) having a V.sub.DS characteristic and a V.sub.GS characteristic; (b) coupling a circuit in series with the at least one FET, the circuit having at least a standby mode and an active mode; and (c) configuring the circuit such that, in the standby mode, no significant current flows through the at least one FET while maintaining essentially the same V.sub.DS characteristic and V.sub.GS characteristic for the at least one FET as during when the circuit is in the active mode, thereby eliminating or reducing changes in accumulated charge.

16. The method of claim 10, 11, 13, or 15, wherein the SOI substrate includes a trap rich layer susceptible to accumulated charge in or near such trap rich layer.

17. The method of claim 10, 11, 13, or 15, further including providing at least one substrate contact near at least one FET.

18. The method of claim 10, 11, 13, or 15, further including providing at least a partial ring of substrate contacts around at least one FET.

Description

DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram of a typical prior art transceiver such as the type that might be used in a cellular telephone.

(2) FIG. 2 is a block diagram of a prior art bias voltage generation circuit.

(3) FIG. 3 is block diagram showing a typical prior art SOI IC structure for a single FET.

(4) FIG. 4 is block diagram showing an improved prior art SOI IC structure for a single FET.

(5) FIG. 5A is a schematic diagram of a first embodiment of the present invention that stabilizes V.sub.DS of a FET when in a standby mode.

(6) FIG. 5B is a schematic of one circuit for generating V.sub.LOAD for the circuit of FIG. 5A.

(7) FIG. 5C is a schematic diagram of the circuit of FIG. 5A configured in an active (non-standby) mode.

(8) FIG. 5D is a schematic diagram of the circuit of FIG. 5A configured in a standby mode.

(9) FIG. 6A is a schematic diagram of a second embodiment of the present invention that stabilizes V.sub.GS of a FET when in a standby mode.

(10) FIG. 6B is a schematic diagram of the circuit of FIG. 6A, but configured in a standby mode.

(11) FIG. 7A is a schematic diagram of a third embodiment of the present invention that provides a trickle current state for a PFET when in a standby mode.

(12) FIG. 7B is a schematic diagram of a fourth embodiment of the present invention that provides a trickle current state for an NFET when in a standby mode.

(13) FIG. 7C is a schematic diagram of a fifth embodiment of the present invention that provides a trickle current state for an NFET when in a standby mode, utilizing fixed current sources.

(14) FIG. 7D is a schematic diagram of a fourth embodiment of the present invention that provides a trickle current state for a PFET when in a standby mode.

(15) FIG. 8 is a schematic diagram of a current mirror circuit for providing a reference current V.sub.BG/R, such as to the bias generator circuit of FIG. 2.

(16) FIG. 9A is a schematic diagram of a current mirror circuit based on the PFET circuit of FIG. 7A.

(17) FIG. 9B is a schematic diagram of a current mirror circuit based on the NFET circuit of FIG. 7B.

(18) FIG. 10 is a schematic diagram of a current mirror circuit based on the PFET circuit of FIG. 7A having matching drain characteristics.

(19) FIG. 11 is a schematic diagram of a bias circuit based on the NFET circuit of FIG. 7B used in conjunction with a variable bias source-follower circuit.

(20) FIG. 12 is a schematic diagram of a bias circuit based on the NFET circuit of FIG. 7C used in conjunction with a current mirror having a variable current source.

(21) FIG. 13 is block diagram showing an SOI IC structure with a trap rich layer, a BOX insulator layer, and substrate contacts for a single FET.

(22) FIG. 14 is a top plan view of an area of a stylized IC that includes twelve example circuits (e.g., current mirrors for bias circuits of a power amplifier).

(23) FIG. 15 is a top plan view of an area of a stylized IC that includes twelve example circuits surrounded by a plurality of S-contacts.

(24) FIG. 16 is a process flow diagram showing a first method for eliminating or reducing changes in accumulated charge in an integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate.

(25) FIG. 17 is a process flow diagram showing a second method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of an integrated circuit susceptible to accumulated charge.

(26) FIG. 18 is a process flow diagram showing a third method for eliminating or reducing changes in accumulated charge in an integrated circuit susceptible to accumulated charge and fabricated on an SOI substrate.

(27) FIG. 19 is a process flow diagram showing a fourth method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of an integrated circuit susceptible to accumulated charge.

(28) FIG. 20 is a process flow diagram showing a fifth method for eliminating or reducing changes in accumulated charge in an integrated circuit susceptible to accumulated charge and fabricated on an SOI substrate.

(29) FIG. 21 is a process flow diagram showing a sixth method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of an integrated circuit susceptible to accumulated charge.

(30) FIG. 22 is a process flow diagram showing a seventh method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of an integrated circuit susceptible to accumulated charge.

(31) FIG. 23 is a process flow diagram showing an eighth method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge.

(32) FIG. 24 is a process flow diagram 2400 showing a ninth method for eliminating or reducing changes in accumulated charge in an integrated circuit susceptible to accumulated charge and fabricated as part of an integrated circuit on a silicon-on-insulator (SOI) substrate.

(33) Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

(34) The invention encompasses several types of radio frequency (RF) integrated circuits (ICs) that avoid or mitigate creation of accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer, by avoiding a fully OFF state for at least some field effect transistors (FETs) within the circuit. By keeping the standby operating conditions of such critical FETs at the active state or as close to the active state as possible, accumulated charge is stabilized at a near-constant level. An important insight into the functioning of such FETs was the realization that the less that certain node voltages of FETs within an SOI IC change, the more stable the charge that may accumulate as a result of circuit activity in the active layer of an IC.

(35) In specific applications, use of one or more embodiments of the present invention lowers standby power consumption of FETs while enabling a very quick sleep-to-active transition time (e.g., <1 S) and achieving a very stable gain very soon after becoming active (e.g., <0.05 dB gain stability in <30 S).

(36) Notably, embodiments of the invention, particularly the trickle current approach described below, help resolve a number of accumulated charge effects of SOI substrates (particularly SOI substrates having a trap rich layer), including floating body effects.

(37) Fixed V.sub.DS Embodiment

(38) FIG. 5A is a schematic diagram of a first embodiment of the present invention that stabilizes V.sub.DS of a FET when in a standby mode. Shown is a P-type FET M1 coupled between a supply voltage V.sub.DD and a controlled through-path switch S1. The gate of M1 is coupled to either a bias voltage V.sub.BIAS or to a standby voltage V.sub.SB (which may be V.sub.DD) through a controlled gate switch S2. As an example, FET M1 may be a component of a power amplifier bias circuit.

(39) The through-path switch S1 may be switched to connect M1 to either a Load or a pseudo load V.sub.LOAD. V.sub.LOAD may be provided by a voltage supply that is approximately equal to the voltage present on the drain of M1 during active mode operation. FIG. 5B is a schematic of one circuit for generating V.sub.LOAD for the circuit of FIG. 5A. In this example, V.sub.LOAD is generated by a simple resistive divider circuit comprising resistances R1 and R2 series coupled between V.sub.DD and circuit ground. The voltage for V.sub.LOAD depends on V.sub.DD and the ratio of R1 to R2. Other circuitry may be coupled between M1 and V.sub.DD and/or between M1 and the Load. An NFET version of the circuit of FIG. 5A would look similar, but upside down: S1, Load, and V.sub.LOAD would be connected between V.sub.DD and M1, with the source of the NFET version of M1 coupled to circuit ground; the gate of M1 would be switched between V.sub.BIAS and circuit ground, and the drain of M1 would be switched between Load and V.sub.LOAD by S1.

(40) As should be apparent to one of ordinary skill in the art, S1 and S2 may each be implemented as FETs coupled in conventional fashion to function as a single-pole, double throw (SPDT) switch. The difference between M1 and S1/S2 is that M1 is generally modulated by an applied input signal (not shown) and essentially behaves as a variable resistor, while S1 and S2 have two binary states, connecting a common terminal to either a first or a second node (in FIG. 5A, S1 and S2 are drawn as being in a neutral position but both are generally binary).

(41) FIG. 5C is a schematic diagram of the circuit of FIG. 5A configured in an active (non-standby) mode. In this configuration, the state of S1 is set to couple M1 to the Load and the state of S2 is set to couple the gate of M1 to V.sub.BIAS. Accordingly, all currents to the gate of M1 and through M1 (i.e., source-drain current I.sub.Ds) flow normally, and M1 is in an active ON mode.

(42) FIG. 5D is a schematic diagram of the circuit of FIG. 5A configured in a standby mode. In this configuration, the state of S1 is set to couple M1 to V.sub.LOAD and the state of S2 is set to couple the gate of M1 to V.sub.SB, where V.sub.SB is set at a value that will turn all currents OFF. For example, by applying V.sub.SB=V.sub.DD to the gate of M1, the gate-to-source voltage V.sub.GS of M1 becomes 0 V, turning M1 OFF. Since V.sub.LOAD is approximately equal to the voltage present on the drain of M1 during active mode operation, then V.sub.DS across M1 is essentially the same as during the active (non-standby) mode, thus reducing operating point changes to V.sub.DS. Since V.sub.DS of M1 remains essentially unchanged when shifting from the active mode to the standby mode, little or no additional charge can accumulate that would adversely affect the switching characteristics of M1. The result is that M1 can be rapidly returned to the active mode by toggling S1 and S2 back to the configuration shown in FIG. 5C.

(43) Control signals (not shown) for switches S1 and S2 may be provided, for example, from a microprocessor 142, or from dedicated power control circuitry or external circuitry (for example, if M1 is part of a power amplifier IC that does not include all of the circuitry for a complete transceiver).

(44) While FIGS. 5A, 5C, and 5D depict a P-type FET, the same principle applies to an N-type FET: in a standby mode, turn the FET OFF while maintaining essentially the same V.sub.DS as during the active mode, thereby eliminating or reducing changes in accumulated charge.

(45) In summary, this aspect of the invention encompasses an integrated circuit susceptible to accumulated charge and fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer), including at least one FET having a V.sub.DS characteristic and configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS characteristic as during an active mode, thereby eliminating or reducing changes in accumulated charge in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain, or source of the FET).

(46) This aspect of the invention further encompasses a circuit fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer) as part of an integrated circuit susceptible to accumulated charge, the circuit including: at least one FET having a drain, a source, a gate, a V.sub.DS characteristic, and a signal path through the FET between the drain and the source; a first switch coupled to the gate of the FET, configured to switchably couple the gate to one of a bias voltage or a standby voltage source; and a second switch coupled to the signal path of the FET, configured to switchably couple the signal path to one of a load or a pseudo-load voltage source; wherein, in an active mode, the first switch couples the gate of the FET to the bias voltage and the second switch couples the signal path of the FET to the load; and wherein, in a standby mode, the first switch couples the gate of the FET to the standby voltage source and the second switch couples the signal path of the FET to the pseudo-load voltage source, thereby maintaining essentially the same VDS characteristic as during the active mode, and thereby eliminating or reducing changes in accumulated charge in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain, or source of the FET).

(47) Fixed V.sub.GS Embodiment

(48) FIG. 6A is a schematic diagram of a second embodiment of the present invention that stabilizes V.sub.GS of a FET when in a standby mode. Shown is a P-type FET M1 coupled between a supply voltage V.sub.DD and a controlled through-path switch S1, which in turn is coupled to a Load. The gate of M1 is coupled to a bias voltage V.sub.BIAS. S1 may be implemented as a FET coupled in conventional fashion to function as a single-pole, single throw (SPST) switch. Accordingly, S1 has two binary states, a CLOSED state (as shown in FIG. 6A) and an OPEN state (as shown in FIG. 6B). As an example, FET M1 may be a component of a bias circuit for a power amplifier. Further, other circuitry may be coupled between M1 and V.sub.DD and/or between M1 and the Load. An NFET version of the circuit of FIG. 6A would look similar, but upside down: S1 and Load would be between V.sub.DD and the drain of M1, with the source of the NFET version of M1 coupled to circuit ground, the gate of M1 connected to V.sub.BIAS, and the drain of M1 coupled through S1 to Load.

(49) In FIG. 6A, M1 is configured in an active (non-standby) mode. In this configuration, the state of S1 is set to CLOSED, thus coupling M1 to the Load. Accordingly, all currents to the gate of M1 and through M1 (i.e., source-drain current I.sub.DS) flow normally, and M1 is in an active ON mode.

(50) FIG. 6B is a schematic diagram of the circuit of FIG. 6A, but configured in a standby mode. In this configuration, the state of S1 is set to OPEN and hence current cannot flow through M1 to the Load. More particularly, V.sub.DS of M1 is 0 V, and V.sub.GS of M1 does not change, thus reducing operating point changes to V.sub.GS. Since V.sub.GS of M1 remains essentially unchanged when shifting from the active mode to the standby mode, little or no additional charge can accumulate that would adversely affect the switching characteristics of M1. The result is that M1 can be rapidly returned to the active mode by toggling S1 back to the configuration shown in FIG. 6A.

(51) Again, control signals (not shown) for switch S1 may be provided, for example, from a microprocessor 142, or from dedicated power control circuitry or external circuitry. While FIGS. 6A and 6B depict a P-type FET, the same principle applies to an N-type FET: in a standby mode, interrupt current flow (I.sub.DS) through the FET while maintaining essentially the same V.sub.GS as during the active mode, thereby eliminating or reducing changes in accumulated charge.

(52) In summary, this aspect of the invention encompasses an integrated circuit susceptible to accumulated charge and fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer), including at least one FET having a V.sub.GS characteristic and configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS characteristic as during the active mode, thereby eliminating or reducing changes in accumulated charge in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain, or source of the FET).

(53) This aspect of the invention further encompasses a circuit fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer) as part of an integrated circuit susceptible to accumulated charge, the circuit including: at least one FET having a drain, a source, a gate, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source; and a switch coupled to the signal path of the FET, configured to switchably couple the signal path to a load or interrupt current flow through the signal path of the FET; wherein, in an active mode, the switch couples the signal path of the FET to the load; and wherein, in a standby mode, the switch interrupts current flow through the signal path of the FET, thereby maintaining essentially the same V.sub.GS characteristic as during the active mode, and thereby eliminating or reducing changes in accumulated charge in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain, or source of the FET).

(54) Trickle Current Embodiment

(55) In the first and second embodiments described above, either V.sub.GS or V.sub.DS was set to essentially 0 V to turn current flow through a FET OFF or interrupt such current flow. However, to meet a particular power consumption specification, a FET does not necessarily have to be shut completely OFF or have all current flow interrupted; instead, the FET can be switched into a very low current state (a trickle current state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Essentially, trickle current embodiments of the invention allow enough current to pass through a FET to maintain an active conduction channel in the FET. In contrast, if a FET is shut OFF completely, the conduction channel is no longer formed and needs to be re-formed when bring the FET out of a standby mode. Effectively, a trickle current mode FET circuit passes just barely enough current to keep the conduction channel active and the FET ready to turn ON when transitioning from the standby mode to the active mode. For example, a trickle current in standby mode of less than 1/1,000 of the active mode current will suffice for many applications, while in other applications, a trickle current in standby mode of less than 1/10,000 or even 1/100,000 of the active mode current may be more useful. As another example, in one power amplifier bias circuit, the active mode current consumption was about 10 mA, while the standby mode current consumption was in the range of about 0.1-1 A.

(56) FIG. 7A is a schematic diagram of a third embodiment of the present invention that provides a trickle current state for a PFET when in a standby mode. Shown is a P-type FET M1 coupled between a supply voltage V.sub.DD and a controlled through-path switch S1. The gate of M1 is coupled to a bias voltage V.sub.BIAS. Also coupled to the gate of the M1 PFET is a feedback voltage 702 from the drain of M1 that provides control over the V.sub.GS of M1; the feedback voltage 702 may be controlled or modified in some applications by optional circuitry 704 (an example of one such control circuit is shown in FIG. 8). Note that the feedback voltage 702 may be V.sub.BIAS; that is, no external bias voltage is applied to the gate of M1, just the feedback voltage 702. As in the above examples, FET M1 may be a component of a power amplifier bias circuit.

(57) The through-path switch S1 may be switched to connect M1 to either an active mode resistance R.sub.L (which may be provided by a Load) or a standby mode resistance R.sub.SB. As in the embodiments described above, S1 may be implemented as FETs coupled in conventional fashion to function as a single-pole, double throw (SPDT) switch such that S1 has two binary states, connecting a common terminal to either a first or a second node (S1 is drawn as being in a neutral position but is generally binary). Other circuitry may be coupled between M1 and V.sub.DD and/or between M1 and R.sub.L.

(58) When the circuit of FIG. 7A is configured in an active (non-standby) mode, the state of S1 is set to couple M1 to R.sub.L. Accordingly, current through M1 flows normally, and M1 is in an active ON mode. When the circuit of FIG. 7A is configured in a standby mode, the state of S1 is set to couple M1 to R.sub.SB. Current through M1 is primarily controlled by the gate of M1. When R.sub.L is changed to R.sub.SB, I.sub.DS must necessarily change, which happens automatically by the concurrent change to the V.sub.GS of M1 by means of the feedback voltage 702 (if V.sub.BIAS was a fixed value and R.sub.L was switched to R.sub.SB, VAS would be near 0 V because the normal mode I.sub.DSR.sub.SB is much greater than V.sub.DD).

(59) The resistance of R.sub.SB should be substantially greater than the resistance of R.sub.L so as to impede the flow of current through M1 down to a trickle. In general, R.sub.SB should have some repeatedly achievable resistance value (taking into account PVT affects) such that the trickle current is above the leakage current of M1. For example, in some embodiments, the ratio of resistances of R.sub.SB to R.sub.L ranges from approximately 100:1 to approximately 1000:1. Accordingly, because a small amount of trickle current continues to flow through M1 when R.sub.SB is switched into circuit, M1 is still active but at much diminished power and speed levels.

(60) FIG. 7B is a schematic diagram of a fourth embodiment of the present invention that provides a trickle current state for an NFET when in a standby mode. Shown is an N-type FET M1 coupled between circuit ground and a controlled through-path switch S1 (S1 is drawn as being in a neutral position but is generally binary). The gate of M1 is coupled to a bias voltage V.sub.BIAS. Also coupled to the gate of the M1 NFET is a feedback voltage 702 from the drain of M1 that provides control over the V.sub.GS of M1; the feedback voltage 702 may be controlled or modified in some applications by optional circuitry 704. Again note that V.sub.BIAS may be entirely provided by the feedback voltage 702.

(61) The through-path switch S1 may be switched to connect M1 to V.sub.DD through either an active resistance R.sub.L (which may be provided by a Load) or a standby mode resistance R.sub.SB. When the circuit of FIG. 7B is configured in an active (non-standby) mode, the state of S1 is set to couple M1 to R.sub.L. Accordingly, current through M1 flows normally, and M1 is in an active ON mode. When the circuit of FIG. 7B is configured in a standby mode, the state of S1 is set to couple M1 to V.sub.DD through R.sub.SB, and the V.sub.GS of M1 is changed as a function of the feedback voltage 702, thereby reducing I.sub.DS. Again, the resistance of R.sub.SB should be substantially greater than the resistance of R.sub.L so as to impede the flow of current through M1 down to a trickle. Accordingly, because a small amount of current continues to flow through M1 when R.sub.SB is switched into circuit, M1 is still active but at much diminished power and speed levels.

(62) FIG. 7C is a schematic diagram of a fifth embodiment of the present invention that provides a trickle current state for an NFET when in a standby mode, utilizing fixed current sources. Shown is an N-type FET M1 coupled between circuit ground and a controlled through-path switch S1 (S1 is drawn as being in a neutral position but is generally binary). The gate of M1 is coupled to a bias voltage V.sub.BIAS. Also coupled to the gate of the M1 NFET is a feedback voltage 702 from the drain of M1 that provides control over the V.sub.GS of M1; again, the feedback voltage 702 may be controlled or modified in some applications by optional circuitry 704, and V.sub.BIAS may be entirely provided by the feedback voltage 702.

(63) The through-path switch S1 may be switched to connect M1 either to an active mode current source I.sub.N or to a lower power standby mode current source I.sub.SB. When the circuit of FIG. 7C is configured in an active (non-standby) mode, the state of S1 is set to couple M1 to I.sub.N. Accordingly, current through M1 flows normally, and M1 is in an active ON mode. When the circuit of FIG. 7C is configured in a standby mode, the state of S1 is set to couple M1 to I.sub.SB, and the V.sub.GS of M1 is changed as a function of the feedback voltage 702, thereby reducing I.sub.DS. The current provided by I.sub.SB should be regulated to allow only a trickle of current to flow through M1. Thus, because a small amount of current continues to flow through M1 when I.sub.SB is switched into circuit, M1 is still active but at much diminished power and speed levels.

(64) FIG. 7D is a schematic diagram of a fourth embodiment of the present invention that provides a trickle current state for a PFET when in a standby mode. Shown is a P-type FET M1 coupled between a supply voltage V.sub.DD and a controlled through-path switch S1. The gate of M1 is selectively coupled by switch S2 to a bias voltage V.sub.BIAS or to a trickle voltage V.sub.TRICKLE. As in the above examples, FET M1 may be a component of a power amplifier bias circuit. The embodiments shown in FIGS. 7B and 7C can be similarly configured with a switch S2 to select a bias voltage V.sub.BIAS or a trickle voltage V.sub.TRICKLE rather than use a feedback voltage 702.

(65) The through-path switch S1 may be switched to connect M1 to either an active mode resistance R.sub.L (which may be provided by a Load) or a standby mode resistance R.sub.SB. Switch S2 would be controlled to concurrently select between V.sub.BIAS (for active mode) or V.sub.TRICKLE (for standby mode). As in the embodiments described above, S1 and S2 may each be implemented as FETs coupled in conventional fashion to function as a single-pole, double throw (SPDT) switch such that they have two binary states, connecting a common terminal to either a first or a second node (both S1 and S2 are drawn as being in a neutral position but are generally binary). Other circuitry may be coupled between M1 and V.sub.DD and/or between M1 and R.sub.L.

(66) When the circuit of FIG. 7D is configured in an active (non-standby) mode, the state of S1 is set to couple M1 to R.sub.L and the state of S2 is set to couple V.sub.BIAS to the gate of M1. Accordingly, current through M1 flows normally, and M1 is in an active ON mode. When the circuit of FIG. 7D is configured in a standby mode, the state of S1 is set to couple M1 to R.sub.SB and the state of S2 is set to couple V.sub.TRICKLE to the gate of M1, thereby reducing I.sub.DS.

(67) A common feature of the embodiments of FIGS. 7A-7D is that the switch S1 selectively couples the source-drain signal path to one of an active mode normal current flow path, or to a standby mode trickle current path in which current is either impeded (e.g., by R.sub.SB) or regulated (e.g., by I.sub.SB).

(68) In all of the trickle current embodiments described above, since V.sub.DS and V.sub.GS of M1 change very little when shifting from the active mode to the standby mode, little additional charge can accumulate in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain, or source of the FET). The result is that M1 can be rapidly returned to the active mode by toggling S1 back to the active mode configuration. In all cases, control signals (not shown) for switch S1 may be provided, for example, from a microprocessor 142, or from dedicated power control circuitry or external circuitry.

(69) Regardless of specific implementation, the same principle applies to all trickle current embodiments: in a standby mode, substantially restrict current flow (I.sub.DS) through a FET while keeping both V.sub.GS and V.sub.DS close to their respective active mode operational voltages, thereby reducing changes in accumulated charge.

(70) In summary, this aspect of the invention encompasses an integrated circuit susceptible to accumulated charge and fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer), including at least one FET having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source, and configured such that, in a standby mode, the FET is switched into a very low current state with respect to current flow through the signal path that keeps both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET close to respective active mode operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic, thereby reducing changes in accumulated charge in or near SOI substrate and/or any the trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain, or source of the FET).

(71) This aspect of the invention further encompasses a circuit fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer) as part of an integrated circuit susceptible to accumulated charge, the circuit including: at least one FET having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source; and a switch coupled to the signal path of the FET, configured to switchably couple the signal path to a normal current flow path or to a trickle current path; wherein, in an active mode, the switch couples the signal path of the FET to the normal current flow path; and wherein, in a standby mode, the switch couples the signal path of the FET to the trickle current path such that both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET are close to respective active mode operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic, thereby reducing changes in accumulated charge in or near SOI substrate and/or any the trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain, or source of the FET). The trickle current path may have a high resistance relative to the normal current flow path, and/or the trickle current path may include a regulated current source that allows only a trickle of current to flow through the FET relative to the normal current flow path.

(72) Trickle Current Circuit Applications

(73) The trickle current circuits shown in FIGS. 7A-7D can be used in a wide variety of applications. For example, FIG. 8 is a schematic diagram of a current mirror circuit 800 for providing a reference current V.sub.BG/R, such as to the bias generator circuit 206 of FIG. 2. Based on the PFET circuit of FIG. 7A, a differential amplifier 802 provides an essentially constant bias voltage V.sub.BIAS to M1 and to a current mirror PFET, M2, based on comparing a reference voltage V.sub.BG to the voltage at the drain of M1, V.sub.SENSE. In both cases, a load (resistance) is switched to a much higher value in the standby mode.

(74) As in FIG. 2, the reference voltage V.sub.BG may be, for example, a band-gap voltage reference. As in the example of FIG. 7A, the current mirror circuit 800 can be switched between an active mode (with M1 coupled to resistance R through switch S1) and a trickle current standby mode (with M1 coupled to higher resistance R.sub.SB through switch S1).

(75) FIG. 9A is a schematic diagram of a current mirror circuit 900 based on the PFET circuit of FIG. 7A. FIG. 9B is a schematic diagram of a current mirror circuit 920 based on the NFET circuit of FIG. 7B. In each configuration, FET M1 is self-biased to function as a diode and provides a bias voltage to current mirror FET M2, which is typically sized to be significantly larger than M1 by a scaling factor m; for example, in some embodiments, m=100. In each configuration, FET M3 represents an example load, or a replica device for a power amplifier. A usable voltage is provided at a respective node N, which may be coupled to other circuitry downstream (not shown); for example, each configuration may be useful for biasing a power amplifier FET stack or a low-noise amplifier (LNA) from node N.

(76) In either case, in the low power standby mode (i.e., R.sub.SB is switched into circuit by S1), normal bias current is replaced with a trickle current. The trickle current reduces the voltage change on each FET gate (for example, compared to pulling a gate to ground) when switching between the active mode and the standby mode. The trickle current also reduces voltage changes on FET drains if the normal-mode loads remain connected. Note that many more current mirror stages may be connected to M2, and each will remain in the preferred low power state as well when R.sub.SB is switched into circuit by S1.

(77) FIG. 10 is a schematic diagram of a current mirror circuit having matching drain characteristics. In this example, two SPDT switches, S1a and S1b, are configured to switch in unison (but in opposite directions for the circuit as drawn; both switches are drawn as being in a neutral position but are generally binary). PFET M1 is self-biased to function as a diode. In the normal mode, the drain of PFET M1 is coupled to R0 through S1a, and the drain of current mirror PFET M2 is coupled to a Load through S1b. In the standby mode, the drain of M1 is coupled to R.sub.SB through S1a and the drain of M2 is coupled to R.sub.SB through S1b, thus shorting the drains together.

(78) Shorting the drains together in the low power standby mode limits additional SOI substrate coupling effects because the two FETs act as one device, which means their terminal voltages match and current densities are the same (ignoring possible device mismatch). Upon return to the active mode, the FETs will have the same starting conditions for V.sub.DS and V.sub.GS, which helps active mode current accuracy and settling time (note that the active mode configuration may include a feedback loop, not shown).

(79) In some configurations, separate resistances (e.g., R.sub.SBa and R.sub.SBb) corresponding to switches S1a and S1b may be used to better match the trickle current requirements of other circuitry (not shown) coupled to M1 and/or M2. As one of ordinary skill in the art would understand, the concepts illustrated in FIG. 10 are extensible to NFETs.

(80) FIG. 11 is a schematic diagram of a bias circuit based on the NFET circuit of FIG. 7B used in conjunction with a variable bias source-follower circuit. NFET M1 is self-biased to function as a diode and provides a bias voltage to NFET MN1, which is typically sized to be significantly larger than M1 by a scaling factor m. In this example, the drain of MN1 is controlled by a source-follower NFET MN.sub.SF coupled to a Load. Actual implementations may use stacks of two or more source-follower stages instead of one, as suggested by the dotted line connecting the single illustrated NFET MN.sub.SF to the Load.

(81) The function of switch S1 is as described above for FIG. 7B, coupling resistance R.sub.0 to M1 in the active mode and coupling much higher resistance R.sub.SB to M1 in the standby mode. In the illustrated example, as an added feature, the bias voltage to the gate of MN.sub.SF may also be varied by mode by controlling switch S2 in unison with switch S1 (both switches are drawn as being in a neutral position but are generally binary). In the active mode, switch S2 would be set to supply a normal bias voltage Vb1 to the gate of MN.sub.SF. However, in the standby mode, switch S2 would be set to supply a lower bias voltage Vb2 to the gate of MN.sub.SF. The lower bias voltage Vb2 would keep the drain voltage of MN1 closer to where it would be in the active mode (e.g., just above V.sub.TH for NFET MN1), thereby reducing changes in accumulated charge.

(82) FIG. 12 is a schematic diagram of a bias circuit based on the NFET circuit of FIG. 7C used in conjunction with a current mirror having a variable current source. Standby mode current source I.sub.SB1 and active mode current source I.sub.N1 can be coupled by a switch S1a to a diode D. Similarly, standby mode current source I.sub.SB2 and active mode current source I.sub.N2 can be coupled by a switch S1b to the sources of PFETS M1 and M3. Switches S1a, S1b are drawn as being in a neutral position but are generally binary, and both are configured to switch in unison. PFET M1 is biased by the diode D, and is series coupled to NFET M2, which is self-biased to function as a diode and provides a bias voltage to NFET M4. PFET M3 is self-biased to function as a diode and is series coupled to NFET M4. The output V between M3 and M4 may be used to bias power amplifier circuitry (not shown).

(83) In the normal mode, switches S1a and S1b couple normal current sources I.sub.N1 and I.sub.N2 in-circuit. In the standby mode, switches S1a and S1b couple low power current sources I.sub.SB1 and I.sub.SB2 in-circuit. In the illustrated configuration, to prevent large voltage changes on amplifier input (i.e., large V) when switching between the standby and active modes, the input to the diode D remains biased with a trickle current in the low power standby mode, rather than being discharged to ground.

Summary of Embodiments

(84) More generally, embodiments of the invention encompass an integrated circuit susceptible to accumulated charge and fabricated on an SOI substrate, including: at least one FET having a V.sub.DS characteristic and a V.sub.GS characteristic, and at least one switch coupled to the FET and configured to be set to a standby mode in which no more than a trickle current flows through the at least one FET while maintaining essentially the same V.sub.DS characteristic and V.sub.GS characteristic for the at least one FET as during an active mode, thereby eliminating or reducing changes in accumulated charge. Further, one or more of the embodiments described above may be used in the same IC.

(85) Substrate Stabilization

(86) Additional techniques may optionally be used in conjunction with embodiments of the circuits described above. For example, in some embodiments, it may be useful to create protected areas on an SOI substrate that encompass FETs that are sensitive to accumulated charge effects by surrounding such areas with substrate contacts (S-contacts), such as the type of S-contacts taught in U.S. patent application Ser. No. 14/964,412 referenced above.

(87) An S-contact in the context of an IC structure is a path which provides a resistive conduction path between a contact region at a surface of a layer of the IC structure and a contact region at or near a surface of a high resistivity substrate of the IC structure (high resistivity includes a range of 3,000 to 20,000 or higher ohm-cm; as known to a person skilled in the art, standard SOI process uses substrates with a low resistivity, typically below 1,000 ohm-cm).

(88) For example, FIG. 13 is block diagram showing an SOI IC structure 1300 with a trap rich layer 404, a BOX insulator layer 406, and substrate contacts for a single FET 410. In the illustrated embodiment, which is otherwise similar to FIG. 4, two S-contacts 1302a, 1302b penetrate through corresponding isolation regions 1304 from the active layer 408 to or near the upper surface of the high resistivity substrate 402. The material used for the S-contacts 1302a, 1302b can be any low resistivity conductive material, such as polysilicon and various metals (e.g., tungsten, copper, etc.). In the case of an SOI device, the isolation regions 1304 can be shallow trench isolation (STI) regions. By virtue of penetrating through the isolation regions 1304 within the active layer 408, the S-contacts 1302a, 1302b remain isolated from direct contact with other active regions of the active layer 408. In common practice, the S-contacts 1302a, 1302b are electrically connected, directly or through other circuit elements, to the source S or the gate G of a FET 410; one possible electrical connection is shown by a dotted line 1306 from the source S of the FET 410 to one S-contact 1302a (other possible contacts are not shown here, but are illustrated in U.S. patent application Ser. No. 14/964,412 referenced above). However, as discussed below, the S-contacts 1302a, 1302b may electrically connected to circuit ground or to another known potential.

(89) In the case of SOI substrates having a trap rich layer 404, as shown in FIG. 13, an S-contact 1302a can penetrate through the trap rich layer 404 to make direct contact with the high resistivity substrate 402. Alternatively, since the trap rich layer 404 has some conductivity (and may be as conductive as the high resistivity substrate 402), in some applications an S-contact 1302b can make a resistive contact with the high resistivity substrate 402 by contacting the surface of the trap rich layer 404. In other applications, an S-contact 1302b can penetrate the trap rich layer 404 to a depth sufficient enough to make a resistive contact, through a remaining portion of the thickness of the trap rich layer 404, with the high resistivity substrate 402.

(90) In addition to the purposes taught in U.S. patent application Ser. No. 14/964,412 referenced above, S-contacts can be used in conjunction with embodiments of the invention (such as the embodiments described above) to create protected areas on an IC substrate that encompass FETs that are sensitive to accumulated charge effects. For example, FIG. 14 is a top plan view of an area 1400 of a stylized IC that includes twelve example circuits 1402 of a type susceptible to accumulated charge resulting from the interaction of an unmodified trap rich layer 404 and transient changes of state of FETs comprising such circuits (e.g., current mirrors for bias circuits of a power amplifier). FIG. 15 is a top plan view of an area 1500 of a stylized IC that includes the twelve example circuits 1402 of FIG. 14 surrounded by a plurality of S-contacts 1502. As illustrated, S-contacts 1502 substantially surround each circuit 1402, essentially creating corresponding wells surrounded by S-contact rings (even though not circular). The rings of S-contacts 1502 around the wells reduce substrate impedance and thus settling time of the substrate voltage under the circuits 1402, help in shielding the circuits 1402 from electrical interference (from each other and from other circuits outside the area 1500), help in draining accumulated charge from the high resistivity substrate 402 and/or trap rich layer 404, and help to improve impedance matching for the circuits 1402 within the wells by preventing uneven substrate potential between circuits. However, even a single S-contact near a circuit 1402 may provide a benefit.

(91) Each of the S-contacts 1502 may be electrically connected, directly or through other circuit elements, to the source S or the gate G of a FET. However, when used with embodiments of the present invention, it may be quite beneficial to connect the S-contacts 1502 to circuit ground or to another known potential (even the IC supply voltage, V.sub.DD), to avoid imposing signals on the S-contacts 1502. Such imposed signals may create accumulated charge in the high resistivity substrate 402 and/or in or near the trap layer 404 and/or elsewhere in the FET (e.g., at the gate, drain, or source of the FET), and may arise, e.g., due to varying voltages applied to active layer 408 elements, such as the source S or gate G of a FET. While a static potential may be most beneficial in some applications, in other applications it may be useful to dynamically change the potential applied to the S-contacts 1502, such as by raising or lowering an applied voltage to counteract accumulated charge that arises during some operational phases (e.g., bursts of signal transmissions in an active mode versus essentially quiescent periods during a standby mode). In some applications, it may be useful to purposefully inject charge into the high resistivity substrate 402 and/or the trap layer 404 by biasing the S-contacts 1502 with a suitable voltage signal. When a potential other than circuit ground is desired, it may be useful use a charge pump or similar means to inject offsetting charge, or apply a negative potential, or apply a positive potential that exceeds the voltage of the IC power supply (e.g., greater than V.sub.DD).

(92) The size, number, and spacing of the S-contacts 1502 generally is a matter of design choice. However, to improve transient effects, wells defined by the S-contacts 1502 should be small enough such that there are essentially no gradients under large circuits 1402 that might necessitate additional impedance matching. Accordingly, the size of the S-contact rings should be similar in size to the wells of potential formed by the S-contacts. Note that complete encirclement of each circuit 1402 may not be necessary in all applications, and that a partial ring of S-contacts may suffice. For example, S-contacts may be omitted in some applications for edges of circuits 1402 not shared with other close-by circuits 1402, such as the S-contacts shown within the dotted oval 1506 of FIG. 15. Moreover, while individual island type S-contacts 1502 are illustrated in FIG. 15, S-contacts can be formed as trenches, in known fashion.

(93) If the S-contacts 1502 are biased in some manner, it may be useful to form a guard ring 1508 of S-contacts around the area 1500 to protect other circuitry; S-contact trenches would work particularly well for such a guard ring 1508, which typically would be grounded.

(94) In addition to the methods taught in U.S. patent application Ser. No. 14/964,412 referenced above, a person skilled in the art will know of many fabrication methods to provide S-contacts suitable for the purposes described in this disclosure.

(95) Methods

(96) Another aspect of the invention includes methods for eliminating or reducing changes in accumulated charge in an integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate (particularly an SOI substrate having a trap rich layer), and for eliminating or reducing changes in accumulated charge in a circuit fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer) as part of an integrated circuit susceptible to accumulated charge. Following are a number of examples of such methods.

(97) FIG. 16 is a process flow diagram 1600 showing a first method for eliminating or reducing changes in accumulated charge in an integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate, including: providing at least one field effect transistor (FET) having a V.sub.DS characteristic (STEP 1602); and configuring the at least one FET such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS characteristic as during an active mode, thereby eliminating or reducing changes in accumulated charge (STEP 1604).

(98) FIG. 17 is a process flow diagram 1700 showing a second method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of an integrated circuit susceptible to accumulated charge, including: providing at least one FET having a drain, a source, a gate, a V.sub.DS characteristic, and a signal path through the FET between the drain and the source (STEP 1702); coupling a first switch to the gate of the FET and configuring the first switch to selectively couple the gate to one of a bias voltage or a standby voltage source (STEP 1704); coupling a second switch to the signal path of the FET, and configuring the second switch to selectively couple the signal path to one of a load or a pseudo-load voltage source (STEP 1706); in an active mode, setting the first switch to couple the gate of the FET to the bias voltage and setting the second switch to couple the signal path of the FET to the load (STEP 1708); and in a standby mode, setting the first switch to couple the gate of the FET to the standby voltage source and setting the second switch to couple the signal path of the FET to the pseudo-load voltage source, thereby maintaining essentially the same V.sub.DS characteristic as during the active mode, and thereby eliminating or reducing changes in accumulated charge (STEP 1710).

(99) FIG. 18 is a process flow diagram 1800 showing a third method for eliminating or reducing changes in accumulated charge in an integrated circuit susceptible to accumulated charge and fabricated on an SOI substrate, including: providing at least one FET having a V.sub.GS characteristic (STEP 1802); and configuring the at least one FET such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS characteristic as during an active mode, thereby eliminating or reducing changes in accumulated charge (STEP 1804).

(100) FIG. 19 is a process flow diagram 1900 showing a fourth method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of an integrated circuit susceptible to accumulated charge, including: providing at least one FET having a drain, a source, a gate, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source (STEP 1902); coupling a switch to the signal path of the FET and configuring the switch to selectively couple the signal path to a load or interrupt current flow through the signal path of the FET (STEP 1904); in an active mode, setting the switch to couple the signal path of the FET to the load (STEP 1906); and in a standby mode, setting the switch to interrupt current flow through the signal path of the FET, thereby maintaining essentially the same V.sub.GS characteristic as during the active mode, and thereby eliminating or reducing changes in accumulated charge (STEP 1908).

(101) FIG. 20 is a process flow diagram 2000 showing a fifth method for eliminating or reducing changes in accumulated charge in an integrated circuit susceptible to accumulated charge and fabricated on an SOI substrate, including: providing at least one FET having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source (STEP 2002); and configuring the at least one FET such that, in a standby mode, the FET is switched into a very low current state with respect to current flow through the signal path that keeps both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET close to respective active mode operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic, thereby reducing changes in accumulated charge (STEP 2004).

(102) FIG. 21 is a process flow diagram 2100 showing a sixth method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of an integrated circuit susceptible to accumulated charge, including: providing at least one FET having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source (STEP 2102); coupling a switch to the signal path of the FET and configuring the switch to selectively couple the signal path to a normal current flow path or to a trickle current path (STEP 2104); in an active mode, setting the switch to couple the signal path of the FET to the normal current flow path (STEP 2106); and in a standby mode, setting the switch to couple the signal path of the FET to the trickle current path such that both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET are close to respective active mode operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic, thereby reducing changes in accumulated charge (STEP 2108).

(103) FIG. 22 is a process flow diagram 2200 showing a seventh method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of an integrated circuit susceptible to accumulated charge, including: providing at least one FET having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source (STEP 2202); coupling a switch to the signal path of the FET, configured to selectively couple the signal path to a load resistance or to a high resistance (STEP 2204); in an active mode, setting the switch to couple the signal path of the FET to the load resistance (STEP 2206); and in a standby mode, setting the switch to couple the signal path of the FET to the high resistance, such that both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET are close to respective active mode operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic, thereby reducing changes in accumulated charge (STEP 2208).

(104) FIG. 23 is a process flow diagram 2300 showing an eighth method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on a silicon-on-insulator (SOI) as part of an integrated circuit substrate susceptible to accumulated charge, including: providing at least one FET having a drain, a source, a gate, a V.sub.DS characteristic, a V.sub.GS characteristic, and a signal path through the FET between the drain and the source (STEP 2302); coupling a switch coupled to the signal path of the FET, configured to selectively couple the signal path to a first current source or to a second current source, the second current source providing a lower current than the first current source (STEP 2302); in an active mode, setting the switch to couple the signal path of the FET to the first current source (STEP 2302); and in a standby mode, setting the switch to couple the signal path of the FET to the second current source, such that both the V.sub.GS characteristic and the V.sub.DS characteristic of the FET are close to respective active mode operational voltages for the V.sub.GS characteristic and the V.sub.DS characteristic, thereby reducing changes in accumulated charge (STEP 2302).

(105) FIG. 24 is a process flow diagram 2400 showing a ninth method for eliminating or reducing changes in accumulated charge in an integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate, including: providing at least one field effect transistor (FET) having a V.sub.DS characteristic and a V.sub.GS characteristic (STEP 2402); and configuring the at least one FET such that, in a standby mode, no significant current flows through the FET while maintaining essentially the same V.sub.DS characteristic and V.sub.GS characteristic as during an active mode, thereby eliminating or reducing changes in accumulated charge (STEP 2404).

(106) Other aspects of the above methods may include one or more of the following: the standby mode pseudo-load voltage source outputting a voltage approximately equal to the voltage present on the drain of the FET during active mode operation; the trickle current path having a high resistance relative to the normal current flow path; providing a regulated current source coupled to the trickle current path that allows only a trickle of current to flow through the FET relative to the normal current flow path; the high resistance being at least about 100 times greater than the load resistance; the SOI substrate including a trap rich layer susceptible to accumulated charge in or near such trap rich layer; and/or providing one or more (e.g., at least a partial ring) substrate contacts (S-contacts) near or around at least one FET.

(107) Fabrication Technologies and Options

(108) The term MOSFET, as used in this disclosure, means any field effect transistor (FET) with an insulated gate and comprising a metal or metal-like, insulator, and semiconductor structure. The terms metal or metal-like include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), insulator includes at least one insulating material (such as silicon oxide or other dielectric material), and semiconductor includes at least one semiconductor material.

(109) As should be readily apparent to one of ordinary skill in the art, various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable IC technology (including but not limited to MOSFET and IGFET structures) that exhibits accumulated charge, including (but not limited to) silicon-on-insulator (SOI) and silicon-on-sapphire (SOS).

(110) Voltage levels may be adjusted or voltage and/or logic signal polarities reversed depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially stacking components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functional without significantly altering the functionality of the disclosed circuits.

(111) The term circuit ground includes a reference potential, and is not limited to an earth ground or other hard ground.

(112) A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion.

(113) It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).