Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a trickle current state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

A differential switch circuit includes: a first transistor having a first terminal coupled with a first input terminal, a second terminal coupled with a first output terminal, and a control terminal coupled with a switch signal receiving terminal; a second transistor having a first terminal coupled with a second input terminal, a second terminal coupled with a second output terminal, and a control terminal coupled with the switch signal receiving terminal; a central switch element positioned between the control terminals of the first and second transistors; and a switch element control circuit for controlling the central switch element based on a switch signal. When the switch signal turns on the first and second transistors, the switch element control circuit turns off the central switch element, and when the switch signal turns off the first and second transistors, the switch element control circuit turns on the central switch element.

The present invention relates to a linear regulator with real-time frequency compensation function, which belongs to the technical field of analog integrated circuits. The part of frequency compensation of the present invention includes the dual-frequency compensation networks and compensation transfer switcher, and the pulse delay circuit. The dual-frequency compensation networks and compensation transfer switcher provide the corresponding frequency compensation for linear regulator under two different capacitive loads. The pulse delay circuit generates a set of signals which have a delay related to the switch-pulse signals to control the access of the compensation transfer switcher and capacitive load. The advantages of the present invention are that the circuit structure is simple, without complex feedback control circuits, the excessive power dissipation is extremely low, and it is applied to such special use of linear regulator with switched capacitive load that it can option the loop frequency compensation in real-time to ensure the linear regulator has the optimal stability and load transient response.

Embodiments of the present disclosure relate to a method, apparatus for operating a conduction assembly, a start device, and a computer-readable medium. The conduction assembly is coupled between an AC power supply and an inductive load, and comprises a first switch device and a second switch device which are in anti-series connection, the first switch device comprises a first body diode in anti-parallel connection with the first switch device, and the second switch device comprises a second body diode in anti-parallel connection with the second switch device. The method comprises: conducting the conduction assembly at a first conduction angle in a first cycle; conducting the conduction assembly in a second cycle at a second conduction angle that is greater than the first conduction angle, wherein in the first cycle and second cycle, a turn-off timing of the first switch device or the second switch device in anti-parallel connection with the first body diode or second body diode having a conduction direction the same as a current direction is determined based on the current flowing through the conduction assembly. The method proposed here may reduce the power loss of the soft start circuit.

An apparatus that includes a first device connected to an inductor. The first device includes a first silicon carbide (SiC) junction gate field-effect transistor (JFET), a first SiC schottky barrier diode (SBD) connected to a gate and a drain of the first SiC JFET, and a first silicon (Si) transistor connected to transmit current to a source of the first SiC JFET. An inductor input terminal is connected to the drain of the first SiC JFET.

Embodiments are described for digital forward body biasing CMOS circuits. In an embodiment, a power management unit limits the amount of time for which digital forward body biasing may be implemented. In another embodiment, once a CMOS circuit is put into a full digital forward body bias mode, the CMOS circuit is gradually brought back to a zero forward body bias mode. In another embodiment, charge is shared among biased transistor wells during transition intervals when transitioning from one bias mode to another.

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a trickle current state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

The present invention relates to a linear regulator with real-time frequency compensation function, which belongs to the technical field of analog integrated circuits. The part of frequency compensation of the present invention includes the dual-frequency compensation networks and compensation transfer switcher, and the pulse delay circuit. The dual-frequency compensation networks and compensation transfer switcher provide the corresponding frequency compensation for linear regulator under two different capacitive loads. The pulse delay circuit generates a set of signals which have a delay related to the switch-pulse signals to control the access of the compensation transfer switcher and capacitive load. The advantages of the present invention are that the circuit structure is simple, without complex feedback control circuits, the excessive power dissipation is extremely low, and it is applied to such special use of linear regulator with switched capacitive load that it can option the loop frequency compensation in real-time to ensure the linear regulator has the optimal stability and load transient response.

Disclosed a drive method, a drive circuit for a power switch and a power supply system. During the turning-on period of the power switch, which can be roughly divided into three processes, a current limiting module is used to limit the current flowing through the power switch for preventing current overshoot, a logic control module is used for controlling the current limiting module not to operate before the turning-on period and the control terminal of the power switch is turned off; during the turning-on period, a feedback circuit adjusts the gate voltage of the power switch for controlling the current flowing through the power switch to reach a predetermined limited value quickly and then maintain at the limited value until the power switch is fully turned on. The current limiting module can be employed in various embodiments. According to the disclosure, the current flowing through the power switch can be effectively controlled during the turning-on period, and the driving time for turning on the power switch is decreased.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.