In one embodiment, there is provided a DC output solid contactor assembly having a housing enclosure and a cavity within the enclosure; one or more SOT-227 isolated semiconductor modules and its variants in a stand-alone, parallel or series configuration; a novel drive circuit board mounted on at least one of the modules with input power terminals for coupling to an input control source; and gate impulse output terminals coupling to one or more semiconductor's gate electrodes. The drive circuit includes a voltage priming system that converts input control signal to an isolated and optimal gate driving voltage level; and positive and negative output power terminals for coupling to the electrical load side.

A current control element includes a control electrode, a first electrode, and a second electrode, is an element in which a current flowing from the second electrode to the first electrode is controlled by a voltage or a current between the control electrode and the first electrode, and does not include a built-in PN body diode between the first electrode and the second electrode, a rectifying element can be a Schottky barrier diode, a charge amount of the rectifying element at a time of reverse bias is smaller than an output charge amount of the current control element, an anode of the rectifying element and a cathode of the rectifying element are electrically connected to the auxiliary terminal and the second electrode, respectively, and the control electrode, the first electrode, and the second electrode are electrically connected to the control terminal, the first terminal, and the second terminal, respectively.

A semiconductor device includes a normally-off power transistor integrated in a semiconductor die and a first failsafe pulldown circuit. A gate of the normally-off power transistor is electrically connected to a control terminal of the semiconductor die. The first failsafe pulldown circuit includes a first normally-on pulldown transistor integrated in the semiconductor die and a turn-off time control circuit. A gate of the first normally-on pulldown transistor is electrically connected to a first reference terminal of the semiconductor die. The first normally-on pulldown transistor is configured to pull down the gate of the normally-off power transistor to a voltage below a threshold voltage of the normally-off power transistor when no voltage is applied across the control terminal and the first reference terminal. The turn-off time control circuit is configured to control a turn-off time of the normally-off power transistor.

An ultra-low clamping voltage Surge Protection Module (SPM) is disclosed which utilizes a depletion mode MOSFET (D MOSFET). The SPM may be part of a circuit or a device and includes a primary protection stage and a secondary protection stage, with the D MOSFET being connected between the two stages. The SPM may include a single D MOSFET, dual D MOSFETs, or multiple D MOSFETs and the primary and secondary protection stages may be implemented with a number of different components. The SPM using D MOSFET(s) exhibits improved surge protection over circuits using inductors.

A switching apparatus electrically connects an electrical load to an energy source and contains a main current path which has a switching unit with a circuit breaker, via which the electrical load is connected to the energy source in a supply mode. An auxiliary current path is connected in parallel with the main current path and in which a first switch is arranged. A disconnection mode is performed in which the circuit breaker is open and the electrical load is connected only to the auxiliary current path to reduce electrical energy stored inside the electrical load. A diagnostic mode is also provided, in which the switching unit is open and the electrical load is connected to the energy source only via the auxiliary current path to supply the electrical load. A control unit for activating the diagnostic mode is also provided.

Circuits for providing overcurrent and overvoltage protection are disclosed herein. The circuits feature a depletion mode MOSFET (D MOSFET) as a current limiter, the D MOSFET being connected to a bi-metallic switch, where the bi-metallic switch acts as a temperature sensing circuit breaker. In combination, the D MOSFET and bi-metallic switch are able to limit current to downstream circuit components, thus protecting the components from damage.

A power conversion system is provided. The power conversion system includes a power conversion circuit and N clamping circuits. The power conversion circuit includes an input port, an output port, N switching power conversion units and N−1 storage device. The switching power conversion unit includes a first switch and a second switch. N is an integer larger than 1. Two ends of the storage device have a first node and a second node respectively. The clamping circuit includes an absorbing capacitor and an absorbing diode and has a first terminal, a second terminal and a third terminal. The first and second terminals are electrically connected to two ends of the corresponding second switch respectively. The absorbing capacitor and the absorbing diode are serially coupled between the first and second terminals for absorbing a peak voltage. The third terminal is electrically connected to the corresponding first node or the input port.

A measurement circuit device for a vehicle includes a power transistor and a voltage measurement circuit coupled to the power transistor that measures a voltage across the power transistor. The measurement circuit device also includes a microcontroller that determines a junction temperature using the measured voltage and adjusts a capacity of the power transistor based on the determined junction temperature. In some embodiments, the measurement circuit device may include a clamping device that clamps the voltage across the transistor when the transistor is off. The measurement circuit device may also include an analog-to-digital converter that converts the measured voltage from an analog value to a digital value.

The present disclosure discloses an output circuit having a voltage-withstanding mechanism that includes a PMOS, a NMOS, a voltage-withstanding auxiliary NMOS and a voltage-withstanding auxiliary circuit. The PMOS includes a first source terminal and a first drain terminal coupled to a voltage source and an output terminal and a first gate receiving a first input signal. The NMOS includes a second source terminal and a second drain terminal coupled to a ground terminal and a connection terminal and a second gate receiving a second input signal. The auxiliary NMOS includes a third drain terminal and a third source terminal coupled to the output terminal and the connection terminal. The auxiliary circuit is coupled to the voltage source and a third gate of the auxiliary NMOS and provides a current conducting mechanism and a resistive mechanism respectively when the output terminal is operated at a logic high level and a logic low level.

A bus interface bus is described. A first logical state is conveyed over the bus by a higher voltage level and a second logical state is conveyed by a lower voltage level. An output stage of the interface includes a power transistor configured to drive the lower voltage level onto the bus to convey the second logical state, and a protective device between the power transistor and the bus. The protective device couples the power transistor to the bus when turned on and limits negative voltage excursions at the power transistor when turned off. A control circuit of the interface is configured to turn on the protective device when the bus voltage is above the lower voltage level and to turn off the protective device when the bus voltage is at or below the lower voltage level.