A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal.

An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.

The present invention provides a frequency synthesizer that is switchable at a high speed and includes a few unnecessary frequency components in an output frequency signal. In a frequency synthesizer 1, a DDS 2 operates based on a clock signal to generate a reference frequency signal with a predetermined reference frequency, and clock signal supply units 41 and 42 switch the clock signals that have different clock frequencies to supply to the DDS 2. When the clock signals are switched to operate the DDS 2, the storage unit 12 stores a combination of a clock frequency f.sub.clk, a reference frequency f.sub.c, and a dividing number N in association with an output frequency f.sub.VCO of the frequency synthesizer 1 such that a spurious frequency does not exist within a predetermined frequency range and a dividing number of a variable frequency divider 302 disposed on a PLL circuit 3 is minimum. Setting units 11 and 24 read setting items stored in the storage unit 12 to set respective units.

The present invention is related to a clock generating device for generating an internal clock signal having a frequency correlated with a clock frequency of an external oscillator when the clock frequency of the external oscillator is not specified in advance. A clock generating device 105 comprises a memory 134 and a PLL circuit 120. The memory 134 is configured to store information about a frequency of an external clock signal generated by an external oscillator 200 at a predetermined timing. The PLL circuit 120 generates a second clock signal correlated with a first clock signal based on the information stored in the memory 134.

A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal is generated by a first digital-to-analog converter (DAC) in response to a digital control signal and a bias compensation current signal. The bias compensation current signal is generated by a second DAC in response to a compensation control signal and a bias reference current. A compensation circuit adjusts the compensation control signal during compensation mode in response to a comparison of a frequency of the output signal to a frequency of a reference signal so as to drive the frequency of the output signal toward matching a desired frequency. The bias compensation current signal associated with the frequency match condition during compensation mode is then used during locked loop mode.

A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal is generated by a first digital-to-analog converter (DAC) in response to a digital control signal and a bias compensation current signal. The bias compensation current signal is generated by a second DAC in response to a compensation control signal and a bias reference current. A compensation circuit adjusts the compensation control signal during compensation mode in response to a comparison of a frequency of the output signal to a frequency of a reference signal so as to drive the frequency of the output signal toward matching a desired frequency. The bias compensation current signal associated with the frequency match condition during compensation mode is then used during locked loop mode.

A voltage-controlled oscillator gain measurement system includes a voltage-controlled oscillator, a voltage detector, and a processor. The voltage-controlled oscillator, which is configured in a phase-locked loop circuit, generates an output signal with an output frequency according to a control signal. The control signal is generated according to the output signal divided by a scaling number. The voltage detector is configured to measure a voltage difference of the control signal. The processor adjusts the scaling number to generate an output frequency difference of the output signal, and obtains a reciprocal gain of the voltage-controlled oscillator by dividing the voltage difference by the output frequency difference.

A mobile communication device adapted to perform spur relocation for a digital phase-locked loop includes a receiver to determine a first frequency channel of interest and to identify a first frequency command word corresponding to the first frequency channel of interest. The mobile communication device further includes control logic circuitry to identify a first frequency at which a first fractional spur associated with the first frequency command word starts to occur and to determine whether the identified first frequency is within the first frequency channel of interest. In addition, the mobile communication device includes a programmable feedback divider configured to change the first frequency command word to a second frequency command word, wherein a second fractional spur associated with the second frequency command word occurs at a second frequency outside the first frequency channel of interest.

A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) and digital logic. Preferred embodiments of the invention include circuit-level techniques that provide better spurious tone performance and very low phase noise with lower power dissipation and supply voltage than prior digital PLLs known to the inventors

An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.