An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

A system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock, and includes an active oscillator that generates the reference clock. The active oscillator includes at least one active component. The RX circuit generates a processed RX signal by processing an RX input signal according to the LO signal. The calibration circuit checks a signal characteristic of the processed RX signal by detecting if a calibration tone exists within a receiver bandwidth, set a frequency calibration control output in response to the calibration tone being not found in the receiver bandwidth, and output the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

A system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock, and includes an active oscillator that generates the reference clock. The active oscillator includes at least one active component. The RX circuit generates a processed RX signal by processing an RX input signal according to the LO signal. The calibration circuit checks a signal characteristic of the processed RX signal by detecting if a calibration tone exists within a receiver bandwidth, set a frequency calibration control output in response to the calibration tone being not found in the receiver bandwidth, and output the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

A method determines a pin-to-pin delay between clock signals having integrally related frequencies. The method includes generating a delay code corresponding to a delay between a first signal edge of a first clock signal received by a first node of an integrated circuit and a second signal edge of a second clock signal received by a second node of the integrated circuit. The delay code is based on a first time code corresponding to the first signal edge, a second time code corresponding to the second signal edge, a first skew code, a second skew code, and a period of the first clock signal or the second clock signal. The first clock signal has a first frequency, the second clock signal has a second frequency, and the second frequency is integrally related to the first frequency.

An apparatus is described and includes a current integrating phase interpolator core having a programmable bias current; an inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal comprising a periodic sawtooth waveform therefrom; a digital-to-analog (D/A) converter for setting an input common mode voltage of the inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuit; and a circuit for computing a difference between a first state of the DCD of the clock signal corresponding to the input common mode voltage of the inverter circuit being set to a high voltage and a second state of the DCD of the clock signal corresponding to the input common mode voltage of the inverter circuit being set to a low voltage.

An apparatus is described and includes a current integrating phase interpolator core having a programmable bias current; an inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal comprising a periodic sawtooth waveform therefrom; a digital-to-analog (D/A) converter for setting an input common mode voltage of the inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuit; and a circuit for computing a difference between a first state of the DCD of the clock signal corresponding to the input common mode voltage of the inverter circuit being set to a high voltage and a second state of the DCD of the clock signal corresponding to the input common mode voltage of the inverter circuit being set to a low voltage.

A clock device includes a first phase interpolator circuit, a detector circuit, and a digital controller circuitry. The first phase interpolator circuit generates a second reference clock signal according to a first control signal and at least one first reference clock signal. The detector circuit generates an error signal according to a difference between a receiver signal and the second reference clock signal, in which the receiver signal is a receiver clock signal from a receiver circuit or an input signal that has been equalized by the receiver circuit. The digital controller circuitry generates the first control signal and a second control signal according to the error signal, and updates the second control signal according to a change of the first control signal, in which the second control signal is for generating a transmitter clock signal of a transmitter circuit.

A time-to-digital converter (TDC) circuitry for converting a phase difference between an input reference signal and an input clock signal to a digitally represented output signal. The TDC circuitry comprises multiple constituent TDCs, a reference signal provider, and a digital signal combiner. Each TDC is configured to convert a phase difference between a constituent reference signal and a constituent clock signal to a digitally represented constituent output signal. The reference signal provider is configured to provide the respective constituent reference signals to each of the TDCs. In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner is configured to provide the digitally represented output signal based on the digitally represented constituent output signals of the TDCs.

A time-to-digital converter (TDC) circuitry for converting a phase difference between an input reference signal and an input clock signal to a digitally represented output signal. The TDC circuitry comprises multiple constituent TDCs, a reference signal provider, and a digital signal combiner. Each TDC is configured to convert a phase difference between a constituent reference signal and a constituent clock signal to a digitally represented constituent output signal. The reference signal provider is configured to provide the respective constituent reference signals to each of the TDCs. In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner is configured to provide the digitally represented output signal based on the digitally represented constituent output signals of the TDCs.