This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP. The SIP can be configured for various applications based on a variety of inputs and control mechanisms.

An N-bit type charge redistribution analog-to-digital conversion device includes an input terminal configured to receive an input signal and coupled via a line to an output terminal. The output terminal is configured to be coupled to a comparator. The device further includes three reference potential sources of different values and a network of capacitors, where a first terminal of each capacitor is coupled to the line, and where a second terminal of each capacitor is coupled to switching circuit configured for coupling the second terminal of each capacitor to one of the reference potentials.

There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by adding the second digital signal and the filtered first digital signal, wherein the first ADC circuit comprises an anti-aliasing filter. Furthermore, a corresponding method and an automobile radar system are described.

Input stages for an analog to digital converter wherein charge for charging parasitic capacitances in the input stage, and particularly in the input switch is sourced from a node which means that it does not have to pass through the input RC filter. This has the effect that the input RC filter can be of lower bandwidth, and/or have a larger resistor value, with the consequent result that there is lower power dissipation in the ADC drive circuitry. In one example this effect is realized by providing a separate input into which charge to charge the parasitic capacitances can be fed from external circuitry. In another example an operational amplifier having high (ideally infinite) input impedance can be used to feed charge to the input switch from the input to the RC filter, or from the node between the resistor and capacitor of the filter, again without unsettling the filter.

An analog conditioning circuit and a corresponding method for processing an analog input signal provide a conditioned analog signal for input into an analog processing circuit. The analog conditioning circuit comprises a main signal path between an input for receiving the analog input signal and an output for outputting the conditioned analog signal, wherein the transfer function of the main signal path is constrained by a transfer function requirement associated with the analog processing circuit; and a feedforward signal path comprising a first filtering block configured to attenuate desired frequencies of a first signal derived from the analog input signal to provide a filtered analog signal; wherein the feedforward signal path is configured to input the filtered analog signal into the main signal path such that the filtered analog signal is subtracted from a second signal derived from the analog input signal to provide the conditioned analog signal.

Techniques and apparatus for alias rejection in analog-to-digital converters (ADCs), in which only a portion of the ADC is operated at a higher sampling rate than other portions of the ADC, thereby preventing aliasing, but saving power. One example ADC circuit generally includes a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.

Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.

A method may include, for a signal path comprising a passive antialiasing filter sampled by a switched-capacitor front-end, monitoring a change of a first impedance of a resistor of the passive antialiasing filter responsive to an environmental condition relative to a second impedance of a switched capacitor of the switched-capacitor front end and compensating the signal path for a change in gain of the signal path resulting from the change of the first impedance.

The disclosure relates to a method and a device for evaluating a signal. The signal is provided from a signal source via a signal conditioning unit to a microcontroller for signal evaluation. The method includes detecting the signal from the signal source and transmitting the signal to the signal conditioning unit, which has an anti-aliasing filter. The method also includes filtering the signal by the anti-aliasing filter, which is set on the basis of the signal to be detected and providing the filtered signal to the microcontroller. The method also includes processing and evaluating the filtered signal in the microcontroller.

The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.