A sensor arrangement includes a switchable voltage source having a source output for alternatively providing a first and a second excitation voltage, an integrator having an integrator input and an integrator output, a sensor resistor having a first terminal coupled to the source output, a reference resistor having a first terminal coupled to a second terminal of the sensor resistor and a second terminal coupled to the integrator input, and a comparator having a first comparator input coupled to the integrator output.

The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.

Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches. The mismatches can degrade the quality of the analog output. To extract the mismatches, a transparent dither can be used. The mismatches can be extracted by observing the analog output, and performing a cross-correlation of the observed output with the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the mismatches.

The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.

Noise suppression is achieved by averaging a sequence of repetitive waveforms with correction of frequency distortions, establishing a real time processing of signals. First, the waveforms are processed seriatim, and saved in partitioned memory. Then, the memory contents are merged to form an output digital signal. Initially, an input repetitive signal is sampled with a sampling period T, and divided into K sections along the sampling period so that a k.sup.th section, where 0k<K, coincides with segment [k.Math.T/K, (k1).Math.T/K]. Time displacement detection determines relative positions of trigger pulses and edges of the sampling clock, and the number k of a sampling period section where the trigger pulse appears, keeping k unchanged thereafter. A resultant stream of N.Math.K samples is transmitted through a lowpass filter, followed by decimation by K, to complete the averaging.

Sensor circuits having a filter and methods for filtering a sensor signal are provided. In this case, a passband width of an adjustable low-pass filter or bandpass filter is adjusted on the basis of a comparison of a measure of a signal change of a sensor signal with a threshold value.

A differential mode converter that includes an input mode converter configured to convert an input voltage in a single-ended mode into a first differential voltage and a second differential voltage to be output, the first differential voltage and the second differential voltage being symmetric with respect to a reference voltage and having a form of a square wave; and a chopper configured to receive the first differential voltage and the second differential voltage and determine a first chopping voltage and a second chopping voltage based on the first differential voltage and the second differential voltage to output the first chopping voltage and the second chopping voltage, the first chopping voltage and the second chopping voltage being symmetric with respect to the reference voltage and having a form of a DC voltage.

Apparatus and methods for synchronization of multiple semiconductor dies are provided herein. In certain implementations, a reference clock signal is distributed to two or more semiconductor dies that each include at least one data converter. The two or more dies include a master die that generates a data converter synchronization signal, and at least one slave die that processes the data converter synchronization signal to align timing of data conversion operations across the dies, for instance, to obtain a high degree of timing coherence for digital sampling. In certain implementations, the dies correspond to radar chips of a radar system, and the data converter synchronization signal corresponds to an analog-to-digital converter (ADC) synchronization signal. Additionally, the master radar chip generates a ramp synchronization signal to synchronize transmission sequencing across the radar chips and/or to provide phase alignment of ADC clock signals.

Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency.

This application relates to analog-to-digital converter (ADC) circuitry (200). A time-encoding modulator (TEM 201) has a comparator (104) and a loop filter (105) configured to generate a pulse-width-modulated (PWM) signal (S.sub.PWM) in response to an input signal (S.sub.IN) and a feedback signal (S.sub.FB). A controlled oscillator, such as a VCO (202) receives the PWM signal and generates an output oscillation signal (S.sub.OSC) with a frequency that varies based on a drive signal at a drive node (109), e.g. a drive node of a ring oscillator (107). The controlled oscillator (202) comprises at least one control switch (112) controlled by a switch control signal (S1) generated from the received PWM signal so as to control the drive strength of the drive signal applied to the drive node (109). The feedback signal (S.sub.FB) for the TEM (201) is derived from the controlled oscillator (202) so as to include any timing error between the PWM signal and the switch control signal (S1) applied to said control switch.