In an embodiment a method includes providing an analog signal comprising a first value of a temperature of an object, performing an analog-to-digital conversion of the analog signal using a first analog-to-digital converter (ADC) thereby providing a first digital signal representing an initial digital temperature value, performing an analog-to-digital conversion of the analog signal using a second ADC thereby providing a second digital signal representing a digital reference temperature value, regularly providing the analog signal comprising a successive value of the temperature of the object, performing the analog-to-digital conversion of the analog signal using the second ADC thereby providing the second digital signal representing a successive digital temperature value, calculating a digital delta temperature value according to a difference between the successive digital temperature value and the digital reference temperature value and repeating providing the analog signal, performing the analog-to-digital conversion and calculating the digital delta temperature value as long as the digital delta temperature value lies within a predefined range.

An error correction method and a time-interleaved analog-to-digital converter (TIADC) are provided. The method is applied to a TIADC that includes a plurality of analog-to-digital converters (ADCs), and the method includes: determining whether a current value of a codeword of a first ADC in the plurality of ADCs is within a preset range; when the current value of the codeword of the first ADC is not within the preset range, adjusting a plurality of codewords that are in a one-to-one correspondence with the plurality of ADCs; and controlling a clock frequency division circuit to generate, by using a plurality of adjusted codewords, a plurality of sampling clocks that are in a one-to-one correspondence with the plurality of ADCs. In embodiments of this application, a sampling time-period skew existing between ADCs may be adjusted by adjusting codewords corresponding to the ADCs.

A successive approximation analog-digital (AD) converter and method performed by the converter are provided. The successive approximation AD converter comprises a digital-analog (DA) converter; a comparator which determines a magnitude relation between an input signal and an output signal of the DA converter; and a successive approximation register which generates a first digital signal based on a determination result. The method comprises: switching an operation selection signal from a first logic to a second logic; performing a logical operation so that a digital signal input to the DA converter has a larger value or a smaller value than the first digital signal, when the operation selection signal has transited to the second logic, based on a portion of the determined first digital signal until transition; and inputting the first digital signal to the DA converter when the operation selection signal is the first logic.

Various embodiments relate to a single slope analog to digital converter (ADC), including: a voltage slope generator; a reference voltage generator configured to generate a first reference voltage, a second reference voltage, and a third reference voltage, where the first reference voltage equals the sum of the second reference voltage and the third reference voltage; a first comparator configured to compare a voltage to a voltage output from the voltage slope generator; a first register configured to store a first count based upon the first reference voltage being input into the first comparator; a second register configured to store a second count based upon the second reference voltage being input into the first comparator; a third register configured to store a third count based upon the third reference voltage being input into the first comparator; a fourth register configured to store a fourth count based upon a first input voltage being input into the first comparator, wherein the first input voltage is the voltage to be converted to a digital value by the ADC; and an output circuit configured to calculate a digital value for the first input voltage based upon the first, second, third, and fourth counts.

A single-ended successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) having a first capacitor associated with a most significant bit (MSB) of the output code, and a second capacitor associated with other bit or bits of the output code; and a second DAC having a first capacitor associated with a MSB of the output code, and a second capacitor associated with other bit or bits of the output code. A bottom plate of the first capacitor of the second DAC is connected to a negative reference voltage in all phases.

A successive approximation analog-digital (AD) converter and method performed by the converter are provided. The successive approximation AD converter comprises a digital-analog (DA) converter; a comparator which determines a magnitude relation between an input signal and an output signal of the DA converter; and a successive approximation register which generates a first digital signal based on a determination result. The method comprises: switching an operation selection signal from a first logic to a second logic; performing a logical operation so that a digital signal input to the DA converter has a larger value or a smaller value than the first digital signal, when the operation selection signal has transited to the second logic, based on a portion of the determined first digital signal until transition; and inputting the first digital signal to the DA converter when the operation selection signal is the first logic.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

The value range for which an error in a digital signal can be corrected is expanded. A control unit generates characteristic information indicating the relationship between an input and an output of an A/D converter and sets a value range. The control unit, in a case in which a value indicated by a first digital signal obtained by the A/D converter converting a first analog voltage signal is within the value range, A/D converts the first analog voltage signal and generates corrected digital information on the basis of the first digital signal and characteristic information, and in a case in which a value indicated by the first digital signal is not within the value range, A/D converts the first analog voltage signal and generates corrected digital information on the basis of a second digital signal obtained by the A/D converter converting the second analog voltage signal and characteristic information.

A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.

Performing a temperature measurement operation includes a first phase and a second phase. The first phase includes providing a voltage indicative of a measured temperature to a first input of a comparator, providing a ramp signal to a second input of the comparator, and generating at an output of the comparator, pulses based on a comparison of the first input to the second input of the comparator. The second phase includes providing the voltage indicative of a measured temperature to the second input of the comparator, providing the ramp signal to the first input of the comparator, and generating at an output of the comparator, pulses based on a comparison of the first input to the second input of the comparator. Performing the temperature measurement operation also includes utilizing the pulses generated during the first and second phases to provide a digital indication of the measured temperature.