A digital optical receiver capable of adaptively correcting the linearity of an analog front end unit is provided. The digital optical receiver comprises: a photoelectric conversion unit that converts an optical signal into an analog electric signal and outputs the analog electric signal; an analog front end unit that converts the analog electric signal obtained from the photoelectric conversion unit into a digital electric signal and outputs the digital electric signal; a linearity correction unit that corrects the linearity of the digital electric signal obtained from the analog front end unit; a demodulation processing unit that demodulates a signal by using, as input, the digital electric signal obtained from the linearity correction unit; and a control unit that provides an offset signal to the analog electric signal outputted by the photoelectric conversion unit, obtains monitor information for the result of the provision of the offset signal, and controls the linearity correction unit so that the linearity correction unit corrects the linearity of the digital electric signal obtained from the analog front end unit on the basis of the monitor information.

A method and system for calibrating a time-interleaved digital to analog converter (DAC) provides equalization of frequency response misalignments in sub-DACs forming the DAC. In a calibration mode, test signals are applied to an DAC and output amplitudes and phases of are measured. From the measured values, complex values of the gains of the respective sub-DACs. h.sub.m(F) are determined and a specified target frequency response T(F) for a tandem connection equalizer-DAC is determined. For each of a plurality of test frequencies, complex values of equalizer gains Eq.sub.m are determined from Eq.sub.m(F)=T(F)/h.sub.m(F), to form equalizing frequency responses. Sets of equalizing coefficients C.sub.m(p) pursuant to discrete Fourier transforms on Eq.sub.m(F). In an operation mode, a digital input signal is transformed input into an equalized digital signal E(n) through use of the sets of equalizing coefficients C.sub.m(p).

To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

Methods and systems are provided for handling nonlinearity corrections during analog-to-digital conversions. A system for handling nonlinearity corrections may include a modem configured to receive a communication signal and generate a frequency spectrum of the communication signal, and a digital signal processor (DSP) configured to analyze the frequency spectrum of the communication signal to determine one or more characteristics of the communication signal, which may occur due to a nonlinear device that operates on the communication signal. The DSP may generate a corrected digital signal by applying a compensation signal to a distorted digital signal generated as a result of application of analog-to-digital conversion to the communication signal. The DSP may generate the compensation signal based on nonlinearity estimation and a spectral analysis of the corrected digital signal.

To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.

An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.

A method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection includes randomizing an order of a plurality of unit elements of a DAC, wherein each of the unit elements is controlled by a respective one of a plurality of digital inputs of the DAC. The plurality of digital inputs is sequentially asserted over at least a subset of a full set of the digital inputs to generate a plurality of analog values of an output of the DAC. A first SNDR of the DAC is measured from the plurality of analog values. A maximum SNDR, corresponding to an optimal order, is determined from the first SNDR and at least one previously measured SNDR. The optimal order of the unit elements of the DAC is stored in a memory to define connections between the digital inputs and the respective unit elements based on the optimal order.