A time-to-digital converter (TDC) measures a time interval T.sub.Tot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals T.sub.NOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals T.sub.NOR. A Vernier core for measures a residual time interval T.sub.R where T.sub.R=T.sub.TotmT.sub.NOR to obtain a value for the time interval T.sub.Tot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

A gate driver circuit includes one or more datastores configured to store one or more result registers, timer circuitry configured to generate a timing signal, and logic circuitry. The logic circuitry is configured to drive switching circuitry using a switching signal and determine a triggering point of a first cycle of the switching signal. In response to the determination of the triggering point, the logic circuitry is configured to control, using the switching signal, one or more analog-to-digital converters (ADCs) to store a first data sample at the one or more result registers. In response to a determination that the switching signal does not include a triggering point, the logic circuitry is configured to control, using the timing signal, the one or more ADCs to store a second data sample at the one or more result registers.

A time-to-digital converter (TDC) measures a time interval T.sub.Tot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals T.sub.NOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals T.sub.NOR. A Vernier core for measures a residual time interval T.sub.R where T.sub.R=T.sub.TotmT.sub.NOR to obtain a value for the time interval T.sub.Tot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.

Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.

An AD converter includes a plurality of analog input terminals, a reference signal generation circuit that generates an analog reference signal, a sample-and-hold unit that includes a plurality of sample-and-hold circuits sampling the analog reference signal or one of analog input signals from the analog input terminals, a control unit that controls the sample-and-hold unit, and a conversion unit that converts an output signal from the sample-and-hold unit into a digital signal. The control unit controls the sample-and-hold unit to perform the output operation for analog input signal and the sampling operation for the analog reference signal.

Systems and circuits for feedback control of an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) are described. An example system includes the asynchronous SAR ADC. A timing detector circuit is coupled to the asynchronous SAR ADC to receive one or more internal signals from the asynchronous SAR ADC. The timing detector circuit outputs a timing detector signal representing an internal timing of the SAR ADC. The timing detector signal is generated based on the one or more internal signals. A regulator circuit is coupled to the timing detector circuit to receive the timing detector signal. The regulator circuit is also coupled to the asynchronous SAR ADC to output a feedback signal to the asynchronous SAR ADC. The feedback signal is generated based on the timing detector signal to control the internal timing of the SAR ADC to match a target timing.

According to an embodiment, an analog-to-digital converter includes a detection circuit, a first conversion circuit, a second comparator, a delay control circuit, a control circuit. A detection circuit detects a differential time signal corresponding to a delay time by using a comparison signal and a delay comparison signal. A first conversion circuit generates a differential voltage by performing time-to-voltage conversion on the differential time signal. A second comparator generates a digital delay determination signal by comparing the differential voltage and an adjustment target voltage. A delay control circuit generates a delay control signal controlling the delay time in accordance with a delay determination signal. A control circuit generates a control signal by using the delay comparison signal in an analog-to-digital conversion period.

Device (1), for continuous-time energy calculation of an analog signal, comprising: a continuous-time analog-to-digital converter which is configured to convert the analog signal into a request signal (REQ), and a direction signal (DIR); at least one filtering unit (11), configured to output a filtered output signal (F.sub.out), and comprising a delaying module (12) and a calculating module (15), connected to the delaying module (12) and configured calculate the filtered output signal (F.sub.out).

According to the invention, the device (1) further comprises: at least one pulse combiner (16), connected to the delaying module (12) and configured to output a combined request signal (CREQ); and at least one energy estimator (17), connected to the filtering unit (11) and to the pulse combiner (16), configured to compute a stored energy value (A.sub.out) associated with each pulse of the combined request signal (CREQ).

A device including a first input for receiving an input current, a second input for receiving a reference current, and a first output. The device is designed to compare the input current with the reference current and, on the basis of the comparison, to output an output current