According to an embodiment, an analog-to-digital converter includes a detection circuit, a first conversion circuit, a second comparator, a delay control circuit, a control circuit. A detection circuit detects a differential time signal corresponding to a delay time by using a comparison signal and a delay comparison signal. A first conversion circuit generates a differential voltage by performing time-to-voltage conversion on the differential time signal. A second comparator generates a digital delay determination signal by comparing the differential voltage and an adjustment target voltage. A delay control circuit generates a delay control signal controlling the delay time in accordance with a delay determination signal. A control circuit generates a control signal by using the delay comparison signal in an analog-to-digital conversion period.

Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions.

In described examples, an integrated circuit (IC) includes multiple subcircuits. The subcircuits include a first subcircuit that receives a current and sinks a portion of the current that is responsive to a threshold. In response to the current being greater than the threshold, the first subcircuit provides a difference between the current and the portion to a second subcircuit and asserts a signal corresponding to an ordinality of the first subcircuit. The second subcircuit is configured to repeat the actions with respect to the first subcircuit, with the second subcircuit in place of the first subcircuit and a third subcircuit in place of the second subcircuit, and with the difference in place of the current, in response to the IC comprising the third subcircuit.

Disclosed herein is a method of operating a single slope analog-to-digital converter (ADC), which includes receiving an input signal from a sensor or a ramp signal from a ramp generator according to a state of a switch and sampling the received input or ramp signal, comparing, by a comparator, whether the sampled ramp signal is present in a predetermined input range in a state in which the ramp generator maintains an off state and outputting the comparison result, generating, by a logic part, a flag signal indicating a high or low according to the comparison result by the comparator and providing the flag signal to the ramp generator, and sampling, by the ramp generator, a reference voltage of the comparator according to the flag signal based on an off or on state.

This invention is related to the method providing computation of the signal frequency components in an acceptable accuracy in contravention of the shifts in the phase and the magnitude information caused by asynchronous sampling of the signals in the process of asynchronous sampling of metal detectors wherein the received signal by the receiver unit (4) divided into time intervals, say timing values those are far shorter than the sampling period and correspond to nearest probable sampling of the ADC (6); providing the computation of the sine and cosine coefficients or exponents of time constant coefficients of the said timing value from previously located or dynamically generated coefficient table; resulting the elimination of the requirement of synchronous sampling and the requirement of the signal period is multiple of the sampling period.

A gate driver circuit includes one or more datastores configured to store one or more result registers, timer circuitry configured to generate a timing signal, and logic circuitry. The logic circuitry is configured to drive switching circuitry using a switching signal and determine a triggering point of a first cycle of the switching signal. In response to the determination of the triggering point, the logic circuitry is configured to control, using the switching signal, one or more analog-to-digital converters (ADCs) to store a first data sample at the one or more result registers. In response to a determination that the switching signal does not include a triggering point, the logic circuitry is configured to control, using the timing signal, the one or more ADCs to store a second data sample at the one or more result registers.

A method of optimizing a quantization step size of an analog-to-digital converter (ADC) based on a number of crossbar arrays of a computing device includes: generating a first mapping relationship between the quantization step size of the ADC and a first root mean square error, the first root mean square error reflecting a quantization error and a clipping error, wherein the generating the first graph is based on use of only a single crossbar array; generating a second mapping relationship between the quantization step size of the ADC and a second root mean square error, the second root mean square error reflecting a quantization error, wherein the generating the second mapping is based on a uniform distribution of a total sum of quantization errors; and determining the quantization step size of the ADC based on the first mapping relationship and the second mapping relationship.

A signal processing circuit includes a first current sensor input, a second current sensor input, a voltage sensor input for receiving a sensor voltage, a first selection unit, a second selection unit, a current analog-digital converter (ADC), a voltage ADC, digital processing block, and a current-voltage converter. The first selection unit includes a first current input coupled to the first current sensor input, and a second current input coupled to the second current sensor input. The second selection unit includes a first voltage input coupled to the voltage sensor input and a second voltage input. The current ADC is coupled to a first current output. The voltage ADC is coupled to a voltage output. The digital processing block is coupled to outputs of the current ADC and the voltage ADC. The current-voltage converter is coupled between a second current output and the second voltage input.

Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses for digital control loop of sensor supply.

In some aspects, a transducer of a system may convert an input to an analog signal. An analog-to-digital converter of the system may convert the analog signal to a digital signal. A low-pass filter of the system may filter the digital signal to create a filtered digital signal. The filtering of the digital signal reduces noise near a resonance frequency of the transducer. Numerous other aspects are described.