The disclosed apparatus, structures, and methods are directed to a wireless receiver. The configurations presented herein employ a structure operative to receive a plurality of analog signals, a signal encoder configured to encode the plurality of received analog signals into a single encoded analog composite signal based on a coding scheme operating under a first code rate, a signal reconstruction module configured to segregate and reconstruct the single encoded digital composite signal into a re-encoded digital composite signal in accordance with the coding scheme operating under a second code rate. In addition, a signal decoder configured to decode the digital composite signals based on the coding scheme operating under the second code rate, and to output digital signals, in which each digital signal in the plurality of digital signals corresponds to a respective analog signal of the plurality of received analog signals.

A method for providing back-compatibility for rational sampling rate disparities between two circuitries, comprises: a) providing a Phase Locked Loop (PLL) operating at a rate different than that of the Symbols generator, which is coupled to a Digital to Analog Converter (DAC) or an Analog to Digital Converter (ADC); b) providing an interpolation filter coupled to said converter, which filter is adapted to perform sampling rate conversion operations on the samples using zero-stuffing, filtering, and decimation, or the like computation-saving algorithm; and c) obtaining the sampling of the symbols at the required and compatible rate.

An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M>1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the n.sup.th Nyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the n.sup.th Nyquist zone to the m.sup.th Nyquist zone of the spectrum, where n>m≥1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.

An analog to digital converter (ADC) includes a conversion circuit digitizing an input analog signal to produce an output digital signal. A current generator generates a constant bias current. A current mirror circuit includes an input transistor receiving the constant bias current, an output transistor in a mirroring relationship with the input transistor and generating a variable bias current, and a parallel transistor circuit selectively coupling a parallel transistor in parallel with the input transistor or the output transistor in response to a control signal. The control signal is representative of the conversion rate of the ADC. A buffer generates a common mode voltage for use by the conversion circuit, from the variable bias current.

A report interval mode is selected from one of multiple selectable report interval modes in cases where the preferred sensor sample intervals of multiple applications are different. By using multiple selectable report interval modes some of the problems that occur when a single fixed report interval mode is used can be avoided.

A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.

An analog to digital converter (ADC) sampling time control method includes: grouping, by an electronic control unit, analog sensor signals received from a plurality of sensors based on a similar signal; setting, by the electronic control unit, a sampling time for converting the grouped analog sensor signals into digital signals; and obtaining, by the electronic control unit, a sensor value by converting the grouped analog sensor signals into the digital signals based on the set sampling time.

A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.

A light detection and ranging (lidar) receiver may include a first photodiode, a first amplifier connected to the first photodiode, and a first analog-to-digital converter (ADC) connected to an output of the first amplifier. The lidar receiver may include a second photodiode, a second amplifier connected to the second photodiode, and a second ADC connected to the second amplifier. The lidar may include a processor connected to an output of the first ADC and an output of the second ADC and a direct-current-to-direct-current converter connected to an output of the processor and to the first photodiode and the second photodiode. The processor may determine, based on the output of the first ADC and the output of the second ADC, a first bias to apply to the first photodiode and a second bias to apply to the second photodiode.