The present invention provides a reference voltage buffer comprises a reference voltage generator, a first operational amplifier, a first transistor, a first group of resistors, a first load, a second transistor, a second group of resistors and a second load. In the reference voltage buffer, the first load and the second load use active device to increase the settling time, and the first load, the second load and the reference voltage generator of the reference voltage buffer are resigned to have the same characteristics in response to the temperature variation to overcome the PVT issue, and the first load and the second load of the reference voltage buffer use the open-loop design to have large full-scale of the output reference voltages.

An over/under voltage protection circuit includes a voltage input terminal, a digital-to analog converter, a comparator, and a control circuit. The comparator includes a first input coupled to an output of the digital-to-analog converter, and a second input coupled to the voltage input terminal. The control circuit includes an output coupled to an input of the digital-to-analog converter, and an input coupled to an output of the comparator. The control circuit is configured to set the digital-to-analog converter to generate an overvoltage fault threshold responsive to the output of the comparator indicating that voltage of a signal at the voltage input terminal exceeds a threshold currently generated by the digital-to-analog converter.

A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal according to a decoded digital signal. However, while many unit cells may be generally the same, there may be variations in the gains associated with each unit cell (e.g., based on the locations of the activated unit cells within a unit cell array) amounting to a gain gradient that may cause error in the analog output. As such, a fill order may be set or selected to counter such variation by activating a particular arrangement of unit cells, as opposed to simply the number of unit cells, for a given digital signal. By filling the unit cell array from different sides, spatially and/or temporally, the gain gradient associated with the unit cells may be balanced to reduce error and increase the linearity of the DAC.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2.sup.M1; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors C.sub.u(n/2)*, C.sub.u(n/2+1)* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; 4) obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR. ADC

Successive-approximation-register (SAR) analog-to-digital conversion technique continues to be one of the most popular analog-to-digital conversion techniques, due to their versatility, which allows providing high resolution output or high conversion rates. In addition, SAR analog-to-digital converters (ADC) have a modest circuit complexity that results in low-power dissipation. A SAR ADC is, typically, composed of a single comparator, a bank of capacitors and switches, in addition to, a control digital logic. However, the comparator input capacitance is input-signal dependent, and hence introduces non-linearity to the transfer characteristics of the ADC. A simple technique is devised to significantly reduce this non-linearity, by pre-distorting the sampled-and-held input signal using the same comparator input capacitance.

An operational amplifier includes a first differential input pair, a first switch and a second switch. The first differential input pair includes a first input transistor and a second input transistor. The first input transistor has a gate terminal coupled to an output terminal of the operational amplifier. The second input transistor has a gate terminal. The first switch is coupled between the gate terminal of the first input transistor and the gate terminal of the second input transistor. The second switch is coupled between a first input terminal of the operational amplifier and the gate terminal of the second input transistor.

Embodiments of an analog-to-digital converter (ADC), resistive digital-to-analog converter (DAC) circuits, and methods of operating an ADC are disclosed. In an embodiment, an analog-to-digital converter includes a DAC unit configured to convert a digital code to a first voltage in response to an input voltage of the ADC, a comparator configured to compare the first voltage with a second voltage to generate a comparison output, and a logic circuit configured to generate the digital code, to control the DAC unit based on the comparison output, and to output the digital code as a digital output of the ADC. The DAC unit includes a capacitive DAC and multiple resistive DACs. Each of the resistive DACs is connected to the first voltage through a respective capacitor.

A circuit device includes a transfer gate, a charge compensation circuit, and a control circuit. The control circuit controls the charge compensation circuit. The charge compensation circuit discharges charge from an output node of the transfer gate when a voltage of an input signal to the transfer gate is in a first voltage range at a timing at which the transfer gate is turned off. The charge compensation circuit injects charge into the output node of the transfer gate when a voltage of the input signal to the transfer gate is in a second voltage range lower than that in the first voltage range at a timing at which the transfer gate is turned off.

A display driver includes a D/A converter circuit for outputting a gradation voltage, and an amplifier circuit that is input with a gradation voltage at an input node. The amplifier circuit includes an operational amplifier, resistance provided between the input node and a node, resistance provided between a node and an output node of the operational amplifier, and an adjustment resistance circuit. The adjustment resistance circuit adjusts a first adjustment resistance value, that is a resistance value between a node and an inverting input node of the operational amplifier, and a second adjustment resistance value, that is a resistance value between the node and the inverting input node.