A system including a circuit, including a first preamplifier, a sampling switch, a regenerative latch, and a second preamplifier aligned in a pipelined sequence with the first preamplifier, wherein the first and second preamplifier are associated with dynamic comparator and configured to gain signal utilizing multiple cascaded gains and sample-and-hold stages including a plurality of phases.

A variety of methods, controllers and electric machine systems are described that facilitate pulsed control of electric machines (e.g., electric motors and generators) to improve the machine's energy conversion efficiency. Under selected operating conditions, the electric machine is intermittently driven (pulsed). The pulsed operation causes the output of the electric machine to alternate between a first output level and a second output level that is lower than the first output level. The output levels are selected such that at least one of the electric machine and a system that includes the electric machine has a higher energy conversion efficiency during the pulsed operation than the electric machine would have when operated at a third output level that would be required to drive the electric machine in a continuous manner to deliver the desired output. In some embodiments, the second output level is zero torque.

The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to-digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be solved by an apparatus comprising a sigma-delta modulator and a sample-time-counter, both controlled by a sample clock, a next-sample-time-computation unit configured to compute a sample-time-counter value when a next digital output sample is requested, a sample-computation-trigger unit connected to the next-sample-time-computation unit configured to compare an actual sample-time-counter value with the sample-time-counter value when the next digital output sample is requested and to trigger a computation unit for calculating a next digital sample when requested and by powering off the sigma-delta modulator in intervals where its delivered samples are not used for any computed decimator output sample. The objective is also solved by a method using the aforementioned analog-to-digital converter.

An analog-to-digital converter comprises a sigma-delta modulator; and an ADC filter configured to store a plurality of partial sums as respective entries in a plurality of lookup tables, retrieve at least one of the plurality of partial sums based on an output of the sigma-delta modulator, and calculate a filter output by adding retrieved ones of the plurality of partial sums together.

A delta-sigma (Σ-Δ) modulator and method for reducing nonlinear error and gain error. The Σ-Δmodulator includes: a plurality of sampling capacitors, configured to sample an input voltage or simultaneously sample an input voltage and a reference voltage signal; an operational amplifier; a plurality of switches, configured to select to sample the input voltage and the reference voltage signal; an integrating capacitor, configured to perform integration superposition on the input voltage and the reference voltage signal sampled by the sampling capacitors; and a control assembly, configured to control, to select to sample the reference voltage signal or simultaneously sample the input voltage and the reference voltage signal within a cycle, and to perform clock control on the sampling capacitors that simultaneously sample the input voltage and the reference voltage signal within a next cycle.

Circuitry generates base-to-emitter voltages (Vbe1, Vbe2) of two BJTs biased at different current densities, a base-to-emitter voltage (Vbe) of a BJT biased so Vbe is complementary to absolute temperature and has a curved non-linearity across temperature, and base-to-emitter voltages (Vbe1_c, Vbe2_c) of two BJTs biased by a temperature independent constant current and a current proportional to absolute temperature so Vbe2_c−Vbe1_c has the same but opposite curved non-linearity across temperature as Vbe. A sampling circuit samples these voltages and provides them to inputs of a loop filter. Filter outputs are quantized to produce a bitstream. The sampling circuit: when the received bit of the bitstream is zero, causes integration of Vbe1−Vbe2 to produce a voltage proportional to absolute temperature (αΔVbe); and when the received bit of the bitstream is one, causes integration of Vbe2_c−Vbe_Vbe1_c to produce a negative voltage complementary to absolute temperature −Vbe_c without non-linearity across temperature.

A variety of methods, controllers and electric machine systems are described for pulse control of electric machines (e.g., electric motors and generators). To improve the energy conversion efficiency of the machine, pulse control involves determining if the machine should operate in a continuous mode or pulse mode, and if the latter, defining a magnitude, duty cycle, and frequency for the pulses. One or more tables, indexing by a wide range of speeds and torque requests, is/are used to define the pulsing frequency or a pulsing frequency pattern.

A variety of methods, controllers and electric machine systems are described for pulse control of electric machines (e.g., electric motors and generators). To improve the energy conversion efficiency of the machine, pulse control involves determining if the machine should operate in a continuous mode or pulse mode, and if the latter, defining a magnitude, duty cycle, and frequency for the pulses. One or more tables, indexing by a wide range of speeds and torque requests, is/are used to define the pulsing frequency or a pulsing frequency pattern.

Σ-Δ modulator and method for reducing nonlinear error and gain error. The Σ-Δ modulator includes: a plurality of sampling capacitors, configured to sample an input voltage or simultaneously sample an input voltage and a reference voltage signal; an operational amplifier; a plurality of switches, configured to select to sample the input voltage and the reference voltage signal; an integrating capacitor, configured to perform integration superposition on the input voltage and the reference voltage signal sampled by the sampling capacitors; and a control assembly, configured to control, to select to sample the reference voltage signal or simultaneously sample the input voltage and the reference voltage signal within a cycle, and to perform clock control on the sampling capacitors that simultaneously sample the input voltage and the reference voltage signal within a next cycle. During input sampling, Vref signals of two capacitors are simultaneously sampled to offset an overlarge area of the integrating capacitor, and a pseudo random number is used to control a polling timing of the capacitors to solve a problem of idle tone of a Σ-Δ modulator, so that the area of the integrating capacitor is effectively reduced, thereby reducing manufacturing costs of an integrated circuit and reducing an output swing.

The present disclosure provides a current generation circuit. In one aspect, the circuit includes a current source transistor and a current sink transistor connected to the current source transistor in series, with respective sources of the current source and sink transistors being connected with each other at a common node. A voltage difference between respective gates of the current source and sink transistors defines a current value flowing through the series, the voltage difference being variable such that the current value is either time-dependent or time-independent. Respective drains of the current source and sink transistors provide a high resistance output necessary to provide a current source or sink function thereby rejecting influence of drain variation or error on the current value.