Patent classifications
H03M13/091
BLOCK GROUP LOSS DETERMINING METHOD AND APPARATUS
This application discloses a block group loss determining method and an apparatus. The method includes: A transmit end obtains at least two block groups, and sends the at least two block groups to a receive end. The receive end receives the at least two block groups, obtains a receiving quantity of first block groups between a first boundary block group and a second boundary block group in the at least two code groups, then obtains a target quantity of first block groups between the first boundary block group and the second boundary block group, and determines a quantity of lost block groups based on the receiving quantity and the target quantity.
Byte-based error correction to improve for wireless networks
Improved error correction systems and methods for wireless networks are described herein. A method can include generating a first cyclic redundancy code (CRC) for a payload of a data packet by executing cycles for sets of input bytes from the payload using a CRC algorithm so as to reduce a number of the cycles required to generate the first CRC when compared to generating the first CRC from individual bits of the payload, appending the first CRC to the payload of the data packet, and transmitting the data packet over a wireless link from a source to a sink.
APPARATUS AND METHODS FOR ERROR DETECTION CODING
A first error-detecting code (EDC) is computed based on a first segment of a block of information that is to be encoded, and a second EDC is computed based on at least a second segment of the block of information. The first EDC is masked with a first masking segment and the second EDC with a second masking segment to generate a first masked EDC and a second masked EDC. The first masking segment and the second masking segment are associated with a target receiver of the block of information. A codeword is generated based on a code and an input vector that includes the first segment, the first masked EDC, the second segment, and the second masked EDC. This type of coding could be useful to support early termination of blind detection at a decoder, for example.
Technologies for applying a redundancy encoding scheme to segmented network packets
Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
APPARATUS AND METHOD FOR ENCODING WITH CYCLIC REDUNDANCY CHECK AND POLAR CODE
The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4.sup.th-Generation (4G) communication system such as Long Term Evolution (LTE). An operation method of a receiving device in a wireless system includes receiving a polar codeword generated by a polar code, generating a majority of decoding paths by decoding a bit value corresponding to one index that is selected among a majority of indexes indicating respective bits included in the polar codeword, determining a first candidate group that includes at least one decoding path among the majority of decoding paths, and determining, as a second candidate group, at least one decoding path passing a CRC check among the first candidate group. A number of the at least one decoding path included in the first candidate group is determined based on a result of a CRC check performed prior to the CRC check.
Cyclic redundancy check, CRC, decoding using the inverse CRC generator polynomial
A cyclic redundancy check, CRC, decoder circuit having a K-bit input bit sequence, s, comprising information bits and CRC bits; and at least one processor (P) configured to perform a CRC decode computation and configured to: use an inverse of a predefined CRC generator polynomial that encoded the K-bit input bit sequence, s, to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error. An LUT stores one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial. A set of mod(−K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, wherein an order of the rows in the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.
Cyclic redundancy check device and method
A communication device and associated method is provided. The communication device includes: a controller; a packet buffer, configured to store a current packet segment and a previous packet segment of an incoming packet; and a plurality of cyclic redundancy check (CRC) circuits, wherein each CRC circuit is individually fed with a portion of the current packet segment and/or a portion of the previous packet segment in a respective cycle of the incoming packet, and an initial value, wherein the plurality of CRC circuits are arranged in parallel.
METHOD AND DEVICE FOR CALCULATING A CRC CODE IN PARALLEL
The disclosure relates to a method performed in a cyclic redundancy check, CRC, device for calculating, based on a generator polynomial G(x), a CRC code for a message block. The method comprises receiving n segments of the message block in forward order or in reverse order, wherein at least one segment is received in reverse order; calculating for each of the n segments a respective segment CRC code based on the generator polynomial G(x), wherein each segment CRC is calculated according to the received order of the segment; aligning each of the n segment CRC codes; and calculating the CRC code for the message block by adding together each of the aligned n segment CRC codes. The disclosure also relates to a device, computer program and computer program product.
CRC code calculation circuit and method thereof, and semiconductor device
A CRC code calculation circuit including: an extraction circuit that extracts a calculation target packet that is a target of CRC calculation from a signal frame inputted as a parallel signal of a first bit length; a shift circuit that generates, when a bit length of the calculation target packet does not match an integral multiple of the first bit length, data A of a bit length that is the integral multiple of the first bit length by shifting the calculation target packet such that a last bit of the calculation target packet is positioned at a least significant bit, and adding “0” to a most significant bit side of a head bit of the shifted calculation target packet; and a calculation circuit that generates a CRC code by performing a CRC calculation on the data A based on an initial value “0” stored in a register.
Method and device in UE and base station for wireless communication
The disclosure provides a method and a device in a User Equipment (UE) and a base station for wireless communication. A first node generates a first bit block, performs channel coding and then transmits a first radio signal. The first bit block comprising all bits in a second bit block and all bits in a third bit block is used for an input of the channel coding, and an output of the channel coding is used for generating the first radio signal. A Cyclic Redundancy Check (CRC) bit block of a fourth bit block is used for generating the third bit block. The fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the bits in the fifth bit block are of fixed values, and the fifth bit block is composed of K bits, the K being a positive integer.