Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

According to some embodiments, a method in a wireless device comprises obtaining a set of information bits for wireless transmission and dividing the set of information bits into one or more subsets of information bits. For each subset, generating extra cyclic redundancy check (CRC) bits using a CRC polynomial capable of generating N CRC bits. The extra CRC bits for each subset comprise less than N CRC bits. The method further comprises: generating a final set of N or less CRC bits for the set of information bits using the CRC polynomial; generating a set of coded bits by encoding the set of information bits for wireless transmission, together with the extra CRC bits and the final set of CRC bits, using a polar encoder; and transmitting the set of coded bits using a wireless transmitter.

A data processing method and apparatus. The data process method includes: determining, by a transmitting node, a code block length N.sub.0 for encoding an information bit sequence to be transmitted according to a data characteristic for representing the information bit sequence to be transmitted and a preset parameter corresponding to the data characteristic; performing, by the transmitting node, polar encoding on the information bit sequence to be transmitted according to the code block length N.sub.0; and transmitting, by the transmitting node, a code block obtained through the polar encoding to a receiving node.

A communication apparatus for forward error correction and detection using polar codes comprising a polar encoder that encodes an input vector to output a codeword using a generator matrix of polar code wherein the input vector is a cyclic redundancy check (CRC) codeword of an information block; a memory that stores a frozen set including frozen bit indices and a non-frozen set including non-frozen bit indices sorted in order of error probabilities; and a controller that is configured to take as input the CRC codeword where CRC bits appended to the end of information block and interleave the CRC codeword using at least one of a first interleaver and second interleaver before feeding the CRC codeword to polar encoder such that the first interleaver places at least one CRC bit earlier than its original position in the CRC codeword and a second interleaver selects at least one bit from the CRC codeword whose corresponding index in a parity check matrix of the CRC code has the highest column weight and puts it in the non-frozen bit index with highest error probability.

A device includes serial cyclic redundancy check (CRC) processing circuitry and parallel CRC processing circuitry. The serial CRS processing circuitry, in operation, generates a set of intermediate CRC bits based on a first set of seed bits and input data. The parallel CRC processing circuitry is coupled to the serial CRC processing circuitry, and, in operation, generates, using the set of intermediate CRC bits as a set of parallel seed bits and using null input bits, a set of output CRC bits corresponding to the input data.

Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein.

Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

A cyclic redundancy check (CRC) system includes an input unit, a plurality of CRC engines for 1 byte to n/2 byte, and an output unit. The input unit has a data de-multiplexer for receiving n byte data. The plurality of CRC engines for 1 byte to n/2 byte are connected to the data de-multiplexer for processing demultiplexed n byte data. The output unit has a data multiplexer for providing processed CRC output data. The plurality of CRC engines for 1 byte to n/2 byte are arranged in two columns. A first column includes one or more CRC engines for 1 byte to n/2 byte and a second column includes a CRC engine for n/2 byte.

Technologies related to enhancing security of digital content are described. Linear error correction codes (LECCs) are employed for dual purposes: 1) to obfuscate digital content; and 2) to verify integrity of the digital content. A transmitter computing system obfuscates digital content based upon an obfuscation protocol, wherein the obfuscated digital content includes an LECC. A receiver computing system deobfuscates the digital content by performing the inverse of the obfuscation protocol.

Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.