The disclosure provides a method and a device in a User Equipment (UE) and a base station for wireless communication. A first node generates a first bit block, performs channel coding and then transmits a first radio signal. The first bit block comprising all bits in a second bit block and all bits in a third bit block is used for an input of the channel coding, and an output of the channel coding is used for generating the first radio signal. A Cyclic Redundancy Check (CRC) bit block of a fourth bit block is used for generating the third bit block. The fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the bits in the fifth bit block are of fixed values, and the fifth bit block is composed of K bits, the K being a positive integer.

Embodiments are directed to error resistant logging. A write-ahead log (WAL) for preserving a verifiable record of file system activity may be provided such that the WAL may include a sequence of log blocks that each may include a cyclic redundancy check (CRC) value of a next adjacent log block in the WAL. In response to executing a file system operation associated with payload data, further actions may be performed, including: generating log blocks based on the payload data; generating a log segment that includes the log blocks; modifying a portion of the contents of a head-block of the log segment such that the modified head-block of the log segment has a CRC value that matches a CRC value of a tail-block of the WAL; copying the contents of the modified head-block of the log segment into the tail-block of the WAL.

Systems and methods for multi-stage downlink control information transmission in a manner that supports existing polar codes are provided. In some embodiments, a method of operation of a radio access node in a cellular communications network to transmit multi-stage downlink control information comprises transmitting a first part of a multi-stage downlink control information in a first Orthogonal Frequency Division Multiplexing (OFDM) symbol and transmitting a second part of the multi-stage downlink control information in a second OFDM symbol that is subsequent to the first OFDM symbol. Cyclic Redundancy Check (CRC) bits are attached to the first part of the multi-stage downlink control information and/or CRC bits are attached to the second part of the multi-stage downlink control information. In some embodiments, the first part and/or the second part of the multi-stage downlink control information is encoded using a polar encoder.

Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to methods and apparatus for dynamic frozen polar codes, for example, for control channels. An exemplary method may be performed at the encoder. The method generally includes encoding a stream of bits using a polar code. The encoding includes selecting a first set of channel indices for encoding information bits. The encoding includes selecting a second set of the channel indices smaller than a channel index for a first information bit for encoding fixed frozen bits. The encoding includes selecting remaining channel indices for dynamic frozen (PCF) bits having values based on one or more of the information bits. The method includes transmitting the encoded stream of bits.

A cyclic redundancy check, CRC, computation circuit comprising an input for receiving an input stream having an input bit sequence comprising two or more bits at a time aligned to rows of a CRC generator matrix stored in a Look Up Table, LUT; a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence; wherein the LUT comprises a plurality of addresses wherein at least one of the addresses is configured to store two or more rows of the CRC generator matrix; and the set of parallel processors is configured to: combine LUT data with the input stream by using two or more bits of the aligned input stream to mask the two or more rows of the CRC generator matrix stored in the LUT; and combine generated two or more intermediate parity bit sequences into a single parity bit sequence.

A memory system includes a non-volatile memory and a controller. The controller is configured to, during a writing operation, generate a first error-detecting code from data that is input, perform a predetermined conversion on the data into first conversion data, generate a second error-detecting code from the first conversion data, and store the data, the first error-detecting code, and the second-error detecting code in the non-volatile memory. The controller is configured to during a read operation, read the data, the first error-detecting code, and the second error-detecting code from the non-volatile memory, perform a first error detection on the data using the first error-detecting code, perform the predetermined conversion on the data into second conversion data, perform a second error detection on the second conversion data using the second error-detecting code, and output the second conversion data based on results of the first and second error detections.

A data processing method and apparatus. The data process method includes: determining, by a transmitting node, a code block length N.sub.0 for encoding an information bit sequence to be transmitted according to a data characteristic for representing the information bit sequence to be transmitted and a preset parameter corresponding to the data characteristic; performing, by the transmitting node, polar encoding on the information bit sequence to be transmitted according to the code block length N.sub.0; and transmitting, by the transmitting node, a code block obtained through the polar encoding to a receiving node.

The disclosure provides a method and a device in a User Equipment (UE) and a base station for wireless communication. A first node generates a first bit block, performs channel coding and then transmits a first radio signal. The first bit block comprising all bits in a second bit block and all bits in a third bit block is used for an input of the channel coding, and an output of the channel coding is used for generating the first radio signal. A Cyclic Redundancy Check (CRC) bit block of a fourth bit block is used for generating the third bit block. The fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the bits in the fifth bit block are of fixed values, and the fifth bit block is composed of K bits, the K being a positive integer.

Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

The disclosure proposes a technique for achieving validity decision performance of a suitable level in communication and broadcasting systems using a polar code. The polar code is a channel code in which it is difficult to use a syndrome check due to a successive cancellation (SC)-based decoding operation and coding structure. Accordingly, in the communication of the related art and broadcasting systems using the polar code, a validity check of a decoding result has been performed by using a path-metric (PM) generated during decoding and a concatenated error detection code, such as a cyclic redundancy check (CRC) code. However, it is difficult to achieve target error detection performance only via such methods when the length of the CRC code is short or when input and output lengths of a code are short. In this regard, an embodiment of the disclosure proposes a method for obtaining a Euclidean distance-based metric between a received signal and a decoded signal by using an estimated codeword output bit sequence, and performing post error detection based on this.