A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection/correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.

The present technology includes a controller and a memory system including the same. The controller includes a memory interface configured to receive a codeword from a memory device, and an error correction circuit configured to: perform an error correction decoding operation on the codeword received from the memory interface, compare a number of unsatisfied check nodes (UCNs) detected in the error correction decoding operation with a reference number, perform or stop the error correction decoding operation on the codeword according to a result of comparing the number of UCNs and the reference number, and output a retransmission request signal of the codeword to the memory interface in response to the result, wherein the memory interface requests the codeword to the memory device in response to the retransmission request signal.

One embodiment provides a system and method for facilitating error-correction protection in a storage device. In response to a write request, the system organizes a block of data in a two-dimensional (2D) array, forms a plurality of first-dimension sub-blocks by dividing the 2D array along a first dimension, and forms a plurality of second-dimension sub-blocks by dividing the 2D array along a second dimension. In response to determining that second-dimension error correction code (ECC) encoding is enabled, the system performs second-dimension ECC encoding on the second-dimension sub-blocks to generate a set of second-dimension ECC bits and performs first-dimension ECC encoding on the first-dimension sub-blocks and the second-dimension ECC bits to generate a set of first-dimension ECC bits. The system writes the data block along with the second-dimension ECC bits and the first-dimension ECC bits to the storage device. The data block and the second-dimension ECC bits are mapped to separate physical addresses in the storage device.

A collector included in a data collection apparatus performs data collection to collect data from a PLC. A controller included in the data collection apparatus determines whether the collector is valid depending on whether the collector at a time when an instruction to start the data collection is provided matches the collector at a preset time, and causes the collector to start the data collection in response to the collector being valid.

A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.

One embodiment provides a system and method for facilitating error-correction protection in a storage device. In response to a write request, the system organizes a block of data in a two-dimensional (2D) array, forms a plurality of first-dimension sub-blocks by dividing the 2D array along a first dimension, and forms a plurality of second-dimension sub-blocks by dividing the 2D array along a second dimension. In response to determining that second-dimension error correction code (ECC) encoding is enabled, the system performs second-dimension ECC encoding on the second-dimension sub-blocks to generate a set of second-dimension ECC bits and performs first-dimension ECC encoding on the first-dimension sub-blocks and the second-dimension ECC bits to generate a set of first-dimension ECC bits. The system writes the data block along with the second-dimension ECC bits and the first-dimension ECC bits to the storage device. The data block and the second-dimension ECC bits are mapped to separate physical addresses in the storage device.

In a method for computer-assisted operation of a memory unit, encoded data is saved in the memory unit. The data is retrieved and decoded after retrieval. The memory unit is monitored for errors in that a temporal sequence of computer-assisted checking operations is carried out for the memory unit. For first-time encoding of the data, each required application data set is generated or selected, containing check data segments. For each application data set, the check data segment is occupied by count data, which characterizes the checking operation being implemented. After retrieving and decoding the application data sets, an error is determined when the count data characterizes neither the checking operation being implemented nor the most recent completely implemented checking operation. The check data segment of the relevant application data set is occupied by count data, which characterizes the checking operation being implemented, if no error was determined.

Examples pertaining to bit selection for polar coding incremental-redundancy hybrid automatic repeat request (IR-HARQ) are described. An apparatus (e.g., UE) generates a re-transmission polar code block (CB) in a polar incremental redundancy HARQ (IR-HARQ) procedure. The apparatus then transmits the re-transmission polar CB as a re-transmission of an initial transmission of an initial polar code carrying a plurality of information bits. In generating the re-transmission polar CB, the apparatus selects one or more re-transmission information bits from the plurality of information bits.

According to one general aspect, an apparatus may include a storage element configured to store both data and metadata, wherein each piece of data is associated with and stored with a corresponding piece of metadata. The apparatus may include a controller processor. The controller processor may be configured to, in response to a piece of data being written to the apparatus: generate a piece of metadata that includes a set of parameters to facilitate a at least partial repair of a block information map, and embed the piece of metadata with the corresponding piece of data.

Various aspects of the disclosure relate to encoding information and decoding information. In some aspects, the disclosure relates to an encoder and a decoder for Polar codes with HARQ. If a first transmission of the encoder fails, information bits associated with a lower quality channel may be retransmitted. At the decoder, the resulting decoded retransmitted bits may be used to decode the first transmission by substituting the retransmitted bits for the original corresponding (low quality channel) bits. In some aspects, to decode the first transmission, soft-combining is applied to the decoded retransmitted bits and the original corresponding (low quality channel) bits. In some aspects, CRC bits for a first transmission may be split between a first subset of bits and a second subset of bits. In this case, the second subset of bits and the associated CRC bits may be used for a second transmission (e.g., a retransmission).