Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. One such method includes providing a plurality of data bits in a word to be transmitted such that a bit-order of the plurality of data bits is flipped with respect to hit-order of the word to be transmitted, providing an EDC as one or more least significant bits of the word to be transmitted and adjacent to a most significant bit of the plurality of data bits in the word to be transmitted, converting the word to be transmitted into a transition number, and transmitting the transition number as a sequence of symbols on the multi-wire interface. The EDC may have a length and a known, fixed value, and length selected to enable a decoder to detect or correct one or more symbol errors in the sequence of symbols.

In an example, there is disclosed an apparatus, comprising: a data store comprising a hash table having for at least some rows a hash entry indexed by a hash value, and comprising a hash chain of one or more pointers to a history buffer, and a spill counter; and one or more logic elements, including at least one hardware logic element, comprising a data compressor to: inspect a string0 comprising n bytes at position p in a data file; get the spill counter from a hash entry corresponding to string0; inspect a string1 comprising n bytes at p+k, wherein k is a positive integer; get the spill counter from a hash entry corresponding to string1; determine that the spill counter for string1 is less than the spill counter for string0; and search a chain1 (the hash chain of a hash entry corresponding to string1) for a matching string of size at least n+k with an offset of k.

Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.

A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one or more read commands for memory devices of the memory subsystem. The read command can include address location information. The memory devices include memory arrays with memory locations addressable with the address location information. The memory locations have associated data and internal check bits, where the check bits are generated internally by the memory for error correction. If the memory device is configured for check bit read mode, in response to the read command, it sends the internal check bits associated with the identified address location. If the memory device is not configured check bit read mode, it returns the data in response to the read command without exposing the internal check bits.

In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding N codes that can be operated on as a first portion of (N/2) codes and a second portion of (N/2) codes to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively. In the code matrix, a bitwise XOR of any two codes in the first portion of the code matrix or any two codes in the second portion of the code matrix results in a code that is either not in the code matrix or is in the other portion of the code matrix. Thus, a miscorrected double bit error in one portion causes a bit to be toggled in the other portion instead of creating a triple bit error.

A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a first circuit which is coupled between the memory and the processor, and which includes a parity generating circuit generating a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a second circuit which is coupled between the memory and the processor, and which includes a parity check circuit detecting a presence or an absence of an error of one-bit or two-bits in the read data and the parity read from the memory.

A semiconductor device includes a bitwise operation unit and a storage control unit. The bitwise operation unit performs a bitwise operation on first n-bit (n is an integer) data that is storage object data and second data of an n-bit bit pattern and generates third data of a bit pattern that the number of 1s and the number of 0s are almost the same as each other. The storage control unit stores the third data into a first storage destination of a storage unit and stores fourth data that is the third data or data that is converted into the third data by performing a bitwise operation that has been predetermined in advance on the data into a second storage destination of the storage unit.

A data processing apparatus including a processor and a memory has a parity/ECC encoder circuit and a parity/ECC decoder circuit. The parity/ECC encoder circuit is disposed in a signal path for writing data to the memory, includes a parity generating circuit for generating a parity of a plurality of bits from data to be written, and writes the generated parity together with the data into the memory. The parity/ECC decoder circuit is disposed in a signal path for reading data from the memory and includes a parity check unit. The parity generating circuit is configured so that each of a plurality of bits configuring the data contributes to generation of a parity of at least two bits. Consequently, the parity check unit can detect a two-bit error at high speed.

A parity check circuit may include a first signal combination unit for generating first to N.sup.thcombination signals by combining first to N.sup.th signals, wherein a K.sup.th (K is a natural number of 2KN) combination signal of the first to N.sup.thcombination signals is obtained by combining the first to K.sup.th signals of the first to N.sup.thsignals, a parity check unit for detecting whether an error is present in the first to N.sup.thsignals in response to the N.sup.th combination signal, a second signal combination iO unit for generating first to N.sup.th reconstruction signals by combining the first to N.sup.th combination signals, wherein a K.sup.threconstruction signal of the first to N.sup.threconstruction signals is obtained by combining a (K1).sup.th combination signal and the K.sup.th combination signal of the first to N.sup.thcombination signals, and a signal storage unit for storing the first to N.sup.threconstruction signals.

A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one or more read commands for memory devices of the memory subsystem. The read command can include address location information. The memory devices include memory arrays with memory locations addressable with the address location information. The memory locations have associated data and internal check bits, where the check bits are generated internally by the memory for error correction. If the memory device is configured for check bit read mode, in response to the read command, it sends the internal check bits associated with the identified address location. If the memory device is not configured check bit read mode, it returns the data in response to the read command without exposing the internal check bits.