A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

There is described a multi-mode unrolled decoder. The decoder comprises a master code input configured to receive a polar encoded master code of length N carrying k information bits and Nk frozen bits, decoding resources comprising processing elements and memory elements connected in an unrolled architecture and defining an operation path between the master code input and an output, for decoding a polar encoded code word, at least one constituent code input configured to receive a polar encoded constituent code of length N/p carrying j information bits and N/pj frozen bits, where p is a power of 2, and at least one input multiplexer provided in the operation path to selectively transmit N/p bits of one of the master code and the constituent code to a subset of the decoding resources.

Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of , wherein is equal to raised to the (2.sup.m/41) power, is equal to a raised to the (2.sup.m/2+1) power, and is a primitive element of GF(2.sup.m). In another embodiment, the system receives a (N, N2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

A method for use in a distributed storage system having a plurality of nodes, the method including receiving, at a source node, original data, encoding the original data into plurality of coded fragments using a linear code, transmitting at least a first one of the coded fragments from the source node to a first sink node. The method further includes receiving, at the source node, modified data, calculating, at the source node, a coded difference between the original data and the modified data, transmitting the coded difference from the source node to the first sink node; and recovering, at the first sink node, at least a first portion of the modified data using the coded difference and the at least a first one of the coded fragments.

This application relates to the field of wireless communications technologies, and discloses a polar code encoding method and apparatus, to improve accuracy of reliability calculation and ordering for polarized channels. The method includes: obtaining a first sequence used to encode K to-be-encoded bits, where the first sequence includes sequence numbers of N polarized channels, the sequence numbers of the N polarized channels are arranged in the first sequence based on reliability of the N polarized channels, K is a positive integer, N is a mother code length of a polar code, N is a positive integer power of 2, and KN; selecting sequence numbers of K polarized channels from the first sequence in descending order of reliability; and placing the to-be-encoded bits based on the selected sequence numbers of the K polarized channels, and performing polar code encoding on the to-be-encoded bits.

Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of , wherein is equal to raised to the (2.sup.m/41) power, is equal to a raised to the (2.sup.m/2+1) power, and is a primitive element of GF(2.sup.m). In another embodiment, the system receives a (N, N2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.

Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.