Embodiments of this application provide an information transmission method and an apparatus, to improve transmission reliability. The method includes: obtaining, by a terminal device, a to-be-sent pilot sequence, where the to-be-sent pilot sequence is a Reed-Muller sequence; and sending, by the terminal device, the to-be-sent pilot sequence.

Disclosed are a method for transmitting uplink control information by a terminal in a wireless communication system and a device for supporting the same. More particularly, disclosed are a method for transmitting, by a terminal, uplink control information corresponding to downlink signals received from two base stations communicating with the terminal by different schemes when the two base stations are connected with the terminal by a dual connectivity method, and a device for supporting the same.

Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats. In an exemplary embodiment, an apparatus includes a dynamic acknowledgement (ACK) list allocation circuit that generates a dynamic ACK list that includes one or two most likely ACK candidates, and a top-Q candidate CQI bits detector that dynamically allocates a detection branch to each of the one or two most likely ACK candidates to detect top-Q candidate CQI bits. The apparatus also includes a merger circuit that mergers the top-Q candidate CQI bits detected for the one or two most likely ACK candidates to generate a merged list, a top-Q CQI symbol generator that generates top-Q CQI symbols for the top-Q candidate CQI bits detected for the one or two most likely ACK candidates, and a joint detector that detects transmitted CQI bits and ACK bits.

This disclosure focuses on example embodiments of a classical approach to the problem of quantum error correction in the presence of faults. Linear codes equipped with faulty parity measurements are disclosed. Example definitions of fault tolerance are introduced and embodiments of a fault tolerant scheme are disclosed that reduce the number of parity measurements required compared with Shor method. Such schemes are well suited to be implemented in the classical control device of a quantum computer in order to ensure quantum fault tolerance.

A high speed decoding algorithm that can decode all the information bits simultaneously at the same time, i.e., in parallel. The method of high speed decoding of polar codes includes the steps of transmitting data bits through a second part of communication channels, wherein a receiver is provided to set frozen bits as 0, apply Sc algorithm, and decode remaining bits in parallel.

A method and an apparatus are provided for decoding a polar code. A simplified successive cancellation list (SSCL) decoding tree for the polar code is generated. The SSCL decoding tree includes a plurality of nodes. One or more nodes of the plurality of nodes are identified as employing Reed-Muller codes for decoding. Decoding of received log-likelihood ratios (LLRs) is performed using Reed-Muller codes at the one or more nodes. Hard decision values are output from the one or more nodes.

An apparatus (100) for providing an joint error correction code (140) for a combined data frame (254) comprising first data (112) of a first data channel and second data (122) of a second data channel comprises a first error code generator (110) configured to provide, based on a linear code, information on a first error correction code (114a, 114b) using the first data (112). The apparatus further comprises a second error code generator (120) configured to provide, based on the linear code, information on a second error correction code (124) using the second data (122). The apparatus is configured to provide the joint error correction code (140) using the information on the first error correction code (114a, 114b) and the information on the second error correction code (124).

Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats. In an exemplary embodiment, an apparatus includes a dynamic acknowledgement (ACK) list allocation circuit that generates a dynamic ACK list that includes one or two most likely ACK candidates, and a top-Q candidate CQI bits detector that dynamically allocates a detection branch to each of the one or two most likely ACK candidates to detect top-Q candidate CQI bits. The apparatus also includes a merger circuit that mergers the top-Q candidate CQI bits detected for the one or two most likely ACK candidates to generate a merged list, a top-Q CQI symbol generator that generates top-Q CQI symbols for the top-Q candidate CQI bits detected for the one or two most likely ACK candidates, and a joint detector that detects transmitted CQI bits and ACK bits.

Detection and correction of technical and non-technical errors in smart grid power distribution are described. A system, method and non-transitory computer readable medium having instructions stored therein that, when executed by one or more processors, causes the one or more processors to perform a method for detecting and correcting technical and non-technical power losses in a smart grid that feature the following functions: remotely characterizing and updating the cables impedances, detecting and classifying the types of losses, estimating the technical and non-technical power losses when a check or smart meter is in error, estimating losses due to tapping a power cable by a registered or an unregistered user, and estimating losses due to a cyber attack. Technical errors corrected are impedance and reactance losses in the power distribution. Non-technical errors identified and corrected are no error, check meter in error, smart meter in error, tapping service cables, or cyber attacks.

A high speed decoding algorithm that can decode all the information bits simultaneously at the same time, i.e., in parallel. The method of high speed decoding of polar codes includes the steps of transmitting data bits through a second part of communication channels, wherein a receiver is provided to set frozen bits as 0, apply Sc algorithm, and decode remaining bits in parallel.