A GNSS (Global Navigation Satellite System) receiver apparatus includes a bank of correlators configured to receive in-phase and quadrature versions of a received signal. A code numerical controlled oscillator is configured to determine a code frequency. A GNSS pseudo random noise sequence generator is configured to generate a pseudo random noise sequence at the code frequency set by the code numerical controlled oscillator. A GNSS pseudo random noise delayed sequence generator includes a first shift register and a second shift register. Taps of the shift registers are selectable as a punctual replica, an early replica and a delayed replica of the pseudo random noise sequence. An enable circuit is configured to generate an enable signal coupled to an enable input of the flip-flops, the enable signal operating at a selectable enable frequency.

The invention pertains to methods and apparatus for non-systematic complex coded unique word DFT spread orthogonal frequency division multiplexing.

The invention pertains to methods and apparatus for non-systematic complex coded unique word DFT spread orthogonal frequency division multiplexing.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

A signal acquiring unit (3) performs signal detection and initial synchronization on an output from a RF frontend (2) by performing circular convolution operation using a first code replica corresponding to a case where a ranging code does not change in polarity and a second code replica corresponding to a case where a ranging code changes in polarity. A signal tracking unit (4) performs synchronization tracking using a result of signal acquisition output from the signal acquiring unit (3) as an initial value.

A signal acquiring unit (3) performs signal detection and initial synchronization on an output from a RF frontend (2) by performing circular convolution operation using a first code replica corresponding to a case where a ranging code does not change in polarity and a second code replica corresponding to a case where a ranging code changes in polarity. A signal tracking unit (4) performs synchronization tracking using a result of signal acquisition output from the signal acquiring unit (3) as an initial value.

A multi-channel transceiver includes a phase-locked loop circuit, a first transmitting channel and a second transmitting channel. The phase-locked loop circuit generates a first clock signal set and a second clock signal set with different frequencies. The first transmitting channel includes a first phase adjusting circuit and a first transmitter. The first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first SSCG profile. According to the first spread spectrum clock signal, the first transmitter generates a first serial data. The second transmitting channel includes a second phase adjusting circuit and a second transmitter. The second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second SSCG profile. According to the second spread spectrum clock signal, the second transmitter generates a second serial data.

A multi-channel transceiver includes a phase-locked loop circuit, a first transmitting channel and a second transmitting channel. The phase-locked loop circuit generates a first clock signal set and a second clock signal set with different frequencies. The first transmitting channel includes a first phase adjusting circuit and a first transmitter. The first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first SSCG profile. According to the first spread spectrum clock signal, the first transmitter generates a first serial data. The second transmitting channel includes a second phase adjusting circuit and a second transmitter. The second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second SSCG profile. According to the second spread spectrum clock signal, the second transmitter generates a second serial data.

The present invention discloses methods of accuracy improving for code measurements in GLONASS GNSS receivers. One component of error budget in code measurements of GLONASS receivers is caused by a difference in signal delays arising in the receiver analog Front End and antenna filter on different channel frequencies specific to GLONASS satellites. Methods to compensate for differences in delays for different GLONASS channel frequencies have been proposed using data collected from a GLONASS signals simulator.