Circuits and methods for performing a clock and data recovery are disclosed. In one example, a clock and data recovery circuit is disclosed. The circuit includes a third order digital filter, e.g. a finite state machine (FSM) that includes three accumulators connected in series. Among the three accumulators, a first accumulator receives an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle and accumulates input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle; a second accumulator accumulates the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle; and a third accumulator accumulates the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a clock and data recovery circuit is disclosed. The circuit includes a third order digital filter, e.g. a finite state machine (FSM) that includes three accumulators connected in series. Among the three accumulators, a first accumulator receives an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle and accumulates input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle; a second accumulator accumulates the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle; and a third accumulator accumulates the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a clock and data recovery circuit is disclosed. The circuit includes a third order digital filter, e.g. a finite state machine (FSM) that includes three accumulators connected in series. Among the three accumulators, a first accumulator receives an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle and accumulates input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle; a second accumulator accumulates the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle; and a third accumulator accumulates the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a clock and data recovery circuit is disclosed. The circuit includes a third order digital filter, e.g. a finite state machine (FSM) that includes three accumulators connected in series. Among the three accumulators, a first accumulator receives an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle and accumulates input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle; a second accumulator accumulates the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle; and a third accumulator accumulates the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle.

A radio frequency (RF) rake receiver may include a plurality of diversity receive paths, with each diversity receive path including a respective rake receiver despreader, and a tracking loop. The tracking loop may be configured to generate a composite timing signal based upon the rake receiver despreaders, and provide the composite timing signal to the diversity receive paths.

A method for determining an indicator of an amount of noise comprised within a received signal within a satellite communication network or a GNSS involves extracting a received modulating signal from the received signal. An estimate of the transmission delay is determined based on the in-phase component of the modulating signal. A prompt replica of the modulating signal is generated using the estimate of the transmission delay. A prompt quadrature correlation of the quadrature component of the received modulating signal and of the quadrature component of the prompt replica is determined, and the indicator of the amount of noise comprised within the received signal is determined based on the prompt quadrature correlation.

A method of processing offset carrier modulated, OCM, ranging signals in a radionavigation system including a plurality of satellite-borne transmitters and at least one ground-based receiver includes receiving a first radionavigation signal from at least one of the plurality of satellite-borne transmitters and down-converting and digitizing the first radionavigation signal to derive therefrom a first OCM signal SA, receiving a second signal SB synchronously broadcast with the first OCM signal SA, the second signal SB having the same or substantially the same center frequency as the first OCM signal SA, coherently combining the first OCM signal SA with the second signal SB at the receiver to generate a combined signal SC, generating a combined correlation value YC corresponding to a correlation of the combined signal SC with a local replica of the first OCM signal SC, and deriving ranging information based on the combined correlation value YC.

Described herein is a receiver for a navigation system, which receives a navigation signal modulated with a pseudorandom sequence along a line-of-sight path and reflected paths. The receiver includes a delay-locked loop, which generates a local sequence, and a first correlator and a second correlator, which operate in open-loop mode and generate a first correlation signal.

Described herein is a receiver for a navigation system, which receives a navigation signal modulated with a pseudorandom sequence along a line-of-sight path and reflected paths. The receiver includes a delay-locked loop, which generates a local sequence, and a first correlator and a second correlator, which operate in open-loop mode and generate a first correlation signal.

A signal receiver divides frequency conversion into multiple steps based on a Log.sub.2(N) number corresponding to the number N of Nyquist zones that are to be covered. This binary structure used Track and Hold (T/H) amplifiers as samplers for wideband frequency conversion where the frequency coverage is defined by a number of cascaded segments. The receiver system includes a plurality of conversion stages coupled in series with one another. Each conversion stage includes a bandpass filter at its input node with a T/H amplifier configured to receive a respective T/H clock signal. Each conversion stage is either bypassed or implemented depending on the frequency bandwidth being processed. Each bandpass filter is configured to have a respective bandwidth range that differs from the bandwidth range of the other bandpass filters. Each T/H amplifier is configured to receive a respective T/H clock input signal.