A method and apparatus for processing global navigation satellite signals, or radar signals, specifies an arrival time of a signal having a shape similar to a known pseudo-random noise sequence (PRN) of rectangular pulses. Two quadrature signals are generated and six correlations are calculated and multiplied by a correlation coefficient. The results of one of quadrature signals are summed and a timing error is estimated. An improved signal arrival time is generated by adding the estimated timing error to the predicted signal arrival time is generated.

A code acquisition module for a direct sequence spread spectrum (DSSS) receiver includes: a Sparse Discrete Fourier transform (SDFT) module configured to perform an SDFT on a finite number of non-uniformly distributed frequencies comprising a preamble of a received DSSS frame to calculate Fourier coefficients for the finite number of non-uniformly distributed frequencies; a multiplier configured to multiply the Fourier coefficients for the finite number of non-uniformly distributed frequencies of the received DSSS frame by complex conjugate Fourier coefficients for the finite number of non-uniformly distributed frequencies to generate a cross-correlation of the received DSSS frame and the complex conjugate Fourier coefficients; and a filter module configured to input the cross-correlation and output a delay estimation for the received DSSS frame.

A code acquisition module for a direct sequence spread spectrum (DSSS) receiver includes: a Sparse Discrete Fourier transform (SDFT) module configured to perform an SDFT on a finite number of non-uniformly distributed frequencies comprising a preamble of a received DSSS frame to calculate Fourier coefficients for the finite number of non-uniformly distributed frequencies; a multiplier configured to multiply the Fourier coefficients for the finite number of non-uniformly distributed frequencies of the received DSSS frame by complex conjugate Fourier coefficients for the finite number of non-uniformly distributed frequencies to generate a cross-correlation of the received DSSS frame and the complex conjugate Fourier coefficients; and a filter module configured to input the cross-correlation and output a delay estimation for the received DSSS frame.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

A Pseudo-Random Noise code generator module is configured to generate PRN codes operating with different navigation standards for use with a GNSS receiver. The generator includes a number of linear shift registers including a respective number of feedback taps and a channel selection network including an output multiplexer. A first register includes a first number of taps and a second register includes a second number of taps. The first register and second register are associated with a respective feedback network to combine signals at the feedback taps to obtain a feedback signal that is selectably fed back through a selection circuit at an input of the respective register. A network can selectably concatenate the first register with the second register.

A Pseudo-Random Noise code generator module is configured to generate PRN codes operating with different navigation standards for use with a GNSS receiver. The generator includes a number of linear shift registers including a respective number of feedback taps and a channel selection network including an output multiplexer. A first register includes a first number of taps and a second register includes a second number of taps. The first register and second register are associated with a respective feedback network to combine signals at the feedback taps to obtain a feedback signal that is selectably fed back through a selection circuit at an input of the respective register. A network can selectably concatenate the first register with the second register.

A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.

A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.

This disclosure relates to a control device for compensating misadjustment of a tunable code loop filter of a portable global navigation satellite system (GNSS) device due to movement of the GNSS device, the control device comprising: a waveform estimator configured to estimate a signal-to-noise ratio (SNR) waveform based on an SNR of a radio signal received by the GNSS device; and a controller configured to tune the code loop filter based on the estimated SNR waveform to compensate for misadjustment of the code loop filter due to movement of the GNSS device.