A chip-to-chip communications circuit which is particularly well-suited for short range communication (less than a few inches) from one integrated circuit (chip) to another is presented. The circuits preferably utilize multi-frequency quadrature amplitude modulation (QAM) mechanisms for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. Differential current mode modulation in the transmitter, and demodulation in the receiver, are utilized which reduce latency and power-consumption while increasing manufacturing yields and resilience to process variations.

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

A multi-cell battery stack includes a microcontroller and a string of battery management and protection IC devices connected to one another in a daisy chain configuration. Each battery management and protection IC device can include a communication interface circuit that includes pairs of differential input signal lines, receivers including respective current comparator circuits to receive differential signals on the differential input signal lines, and transmitters to provide outgoing differential signals on the differential input signal lines. A digital circuit block allows signals to pass between the receivers and transmitters.

A multi-cell battery stack includes a microcontroller and a string of battery management and protection IC devices connected to one another in a daisy chain configuration. Each battery management and protection IC device can include a communication interface circuit includes pairs of differential input signal lines, receivers including respective current comparator circuits to receive differential signals on the differential input signal lines, and transmitters to provide outgoing differential signals on the differential input signal lines. A digital circuit block allows signals to pass between the receivers and transmitters.

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

Disclosed is a receiver that includes a pre-amplifier circuit and an amplifier circuit. The pre-amplifier circuit includes first and second input terminals that receive signals from a transmitter; first and second output terminals that output signals to the amplifier circuit; a first resistor having a first terminal coupled to the first input terminal, and a second terminal coupled to a first node; a second resistor having a first terminal coupled to the second input terminal, and a second terminal coupled to the first node; a third resistor having a first terminal coupled to the first output terminal, and a second terminal coupled to a second node; a fourth resistor having a first terminal coupled to the second output terminal, and a second terminal coupled to the second node; and a switch having a first terminal coupled to the first node, and a second terminal coupled to the second node.

In some embodiments, a communication device configured to receive power and communicate data signals via a differential pair of conductors is provided. The communication device comprises circuitry configured to generate or receive a common mode voltage via the differential pair; and at least one of: circuitry configured to, in response to detecting an edge of an incoming digital signal via an input conductor, transmit an outgoing pair of pulses based on the detected edge via the differential pair; or circuitry configured to detect an incoming pair of pulses via the differential pair and adjust a signal transmitted via an output conductor indicating a logical value based on the incoming pair of pulses.

A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.

Systems and methods for bidirectional communication between a first die and a second die using a shared route are described. The method includes, during a first phase of operation, allowing bidirectional communication between the first die and the second die using the shared route. The method further includes, during a second phase of operation: (1) pausing bidirectional communication between the first die and the second die using the shared route, (2) parking the first transmit driver by coupling an input terminal of the first transmit driver to a voltage level, and (3) parking the second transmit driver by coupling an input terminal of the second transmit driver to the same voltage level, where the voltage level is one of a voltage supply level or a ground level. Additional systems and methods for clock gating of signals that make the bidirectional communication even more efficient are also described.

A continuous time linear equalizer (CTLE), comprising: a first transconductance gain circuit configured to amplify an input voltage signal with a first transconductance gain to generate a first current signal; a second transconductance gain circuit configured to amplify the input voltage signal with a second transconductance gain to generate a second current signal, wherein the second transconductance gain circuit is configured to reuse the first current signal to generate the second current signal; and at least one resistor through which the first current signal and the second current signal flow to generate an output voltage signal.