For example, an apparatus may include a Printed Circuit Board (PCB) including a Ball Grid Array (BGA) on a first side of the PCB, the BGA configured to connect a Surface Mounted Device (SMD) to the PCB; an antenna disposed on a second side of the PCB opposite to the first side, the antenna to communicate a Radio Frequency (RF) signal of the SMD; and an RF transition to transit the RF signal between the BGA and the antenna, the RF transition including a plurality of signal buried-vias; a first plurality of microvias configured to transit the RF signal between the plurality of signal buried-vias and a ball of the BGA, the first plurality of microvias are rotationally misaligned with respect to the plurality of signal buried-vias; and a second plurality of microvias configured to transit the RF signal between the plurality of signal buried-vias and the antenna.

A single-layer redistribution plate functioning as a space translator between a device under testing (“DUT”) and a testing PCB may comprise a hard ceramic plate. A DUT side of the plate may have pads configured to interface with a device under testing. Both sides of the plate may comprise traces, vias, and pads to fan out the DUT pad pattern so that the plate side opposite the DUT side has spatially translated pads configured to interface with the pads on a testing PCB. Fabricating a redistribution plate may comprise calibrating and aligning, laser milling vias, laser milling trenches and pads, copper plating, grinding and polishing, removing residual copper, and coating the copper surfaces.

A circuit board may include a plurality of electrically-conductive layers separated and supported by layers of insulating material laminated together and a via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board, the via comprising a first via portion comprising electrically-conductive material and having a first diameter and a first depth from a surface of the circuit board and a second via portion comprising electrically-conductive material and having a second diameter smaller than the first diameter and a second depth from the first depth.

A low passive intermodulation (PIM) coaxial-to-printed circuit board (PCB) interface and method of constructing the same. According to one aspect, a coaxial-to-PCB interface couples signals between an electrical conductor trace in the PCB and an inner conductor of a coaxial structure having an insulator surrounded by an outer conductor. A metallic cylinder is inserted over the outer conductor of the coaxial structure and positioning the coaxial structure with respect to the PCB so that the outer conductor and insulator of the coaxial structure lie below a lower surface of the PCB. The inner conductor of the coaxial structure is inserted into a via extending from the lower surface of the PCB to an upper surface of the PCB. Solder is deposited in the via to provide an electrically conductive path between the electrical conductor trace of the PCB and the inner conductor of the coaxial structure.

A single-layer redistribution plate functioning as a space translator between a device under testing (“DUT”) and a testing PCB may comprise a hard ceramic plate. A DUT side of the plate may have pads configured to interface with a device under testing. Both sides of the plate may comprise traces, vias, and pads to fan out the DUT pad pattern so that the plate side opposite the DUT side has spatially translated pads configured to interface with the pads on a testing PCB. Fabricating a redistribution plate may comprise calibrating and aligning, laser milling vias, laser milling trenches and pads, copper plating, grinding and polishing, removing residual copper, and coating the copper surfaces.

A circuit board may include a traditional via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board and a slotted via formed within the circuit board proximate to the traditional via, the slotted via comprising an opening through a first surface and a second surface of the circuit board and a layer of conductive material formed on interior walls of the opening.

An information handling system may include a battery, a circuit board, an enclosure, and a control circuit. The circuit board may include at least one electric component, a first electrically conductive pad, and a second electrically conductive pad in proximity to the first electrically conductive pad. The enclosure may be configured to house components of the information handling system including the battery and the circuit board, and the enclosure may include a first member, a second member configured to be mechanically coupled to the first member, and a mechanical component comprising conductive material and configured to electrically short the first electrically conductive pad to the second electrically conductive pad when the first member is mechanically coupled to the second member, and cause electrical isolation of the first electrically conductive pad from the second electrically conductive pad when the first member is mechanically decoupled from the second member. The control circuit may be configured to, when the first electrically conductive pad is shorted to the second electrically conductive pad, cause the at least one electrical component to be electrically coupled to the battery and when the first electrically conductive pad is electrically isolated from the second electrically conductive pad, cause the at least one electrical component to be electrically decoupled from the battery.

An electronic element mounting substrate includes a substrate including a first layer, a second layer located on a lower surface of the first layer, and a third layer located on a lower surface of the second layer, and on which an electronic element is to be mounted. The substrate has a via conductor that passes through the first layer to the third layer in a vertical direction. The substrate includes respective electrical conductor layers located between the respective layers and connected to the via conductor in a plan perspective. Each electrical conductor layer includes a land portion surrounding the via conductor, a clearance portion surrounding the land portion, and a peripheral portion surrounding the clearance portion and electrically insulated from the land portion with the clearance portion interposed between the land portion and the peripheral portion. The first land portion has, in a plan perspective, a first portion overlapping the second land portion, and the first clearance portion has, in a plan perspective, a second portion not overlapping the second clearance portion. The first peripheral portion and the second peripheral portion each have, in a vertical cross-sectional view, an end portion that becomes thinner as a distance from the via conductor increases.

An electronic device including an interposer is provided. The electronic device includes a first circuit board having a first connection terminal formed thereon, an application processor (AP) connected to the first connection terminal and deployed on the first circuit board, an interposer having a via formed therein and having a first surface attached to the first circuit board, the interposer at least partly surrounding at least a partial region of the first circuit board and a first end portion of the via being electrically connected to the first connection terminal, a second circuit board having a second connection terminal formed thereon and attached to a second surface of the interposer in an opposite direction to the first surface, the second connection terminal being electrically connected to a second end portion of the via and the second circuit board forming an inner space together with the first circuit board and the interposer, a communication processor (CP) connected to the second connection terminal and deployed on the second circuit board, and an antenna electrically connected to the CP.

A multilayer circuit board includes a board body including insulator layers stacked upon each other, a first land pattern at the board body to mount a passive component, a second land pattern at the board body to mount an active component, and a heat-dissipation layer between the insulator layers and extending along main surfaces of the insulator layers. The heat-dissipation layer includes a hole extending therethrough in a stacking direction of the insulator layers. In a plan view from the stacking direction, an outer edge of the hole of the heat-dissipation layer is on an outer side of the first land pattern, or overlaps the first land pattern.