A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

A component carrier includes a stack having at least one horizontal electrically conductive layer structure, at least one electrically insulating layer structure, a semiconductor component embedded in the stack, and at least one vertical via being laterally offset from the semiconductor component. The at least one horizontal electrically conductive layer structure electrically connects the vertical via to a bottom main surface of the semiconductor component. The component carrier is configured for a current flow from the vertical via to the horizontal electrically conductive layer structure, from the horizontal electrically conductive layer structure to the bottom main surface of the semiconductor component, from the bottom main surface of the semiconductor component to an upper main surface of the semiconductor component, and from the upper surface of the semiconductor component to the outside of the component carrier.

A method for manufacturing a circuit board including the following steps: providing a flexible double-sided metal-clad laminate including a first metal foil, a flexible dielectric layer, and a second metal foil. A carrier is attached to the second metal foil. A first wiring layer including a first wiring region and a second wiring region is formed by the first metal foil. The first wiring region includes a first connecting pad, and the second wiring region includes a connecting pad. A plurality of rigid dielectric blocks surrounded to form an interval and a first groove exposing the first connecting pad is pressed on the flexible dielectric layer to form a rigid dielectric layer. An electronic component is fixed the first groove. The carrier is removed. The intermediate structure is bent along the interval and pressed. A second wiring layer is formed by the second metal foil.

A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, an interconnect layer electrically connected to the thin film capacitor, and an encapsulating resin layer laminated on the thin film capacitor. The interconnect layer includes a pad protruding from the thin film capacitor. The encapsulating resin layer is a mold resin having a non-photosensitive thermosetting resin as a main component thereof. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad.

An extremely thin copper foil is provided that enables formation of highly fine different wiring patterns with a line/space (L/S) of 10 μm or less/10 μm or less on two sides of the copper foil and is thus usable as an inexpensive and readily processable substitution for silicon and glass interposers. The extremely thin copper foil includes, in sequence, a first extremely thin copper layer, an etching stopper layer, and the second extremely thin copper layer. Two sides of the extremely thin copper foil each have an arithmetic average roughness Ra of 20 nm or less.

Fabric may include one or more conductive strands. An insertion tool may insert an electrical component into the fabric during formation of the fabric. The electrical component may include an electrical device mounted to a substrate and encapsulated by a protective structure. An interconnect structure such as a metal via or printed circuit layers may pass through an opening in the protective structure and may be used to couple a conductive strand to a contact pad on the substrate. The protective structure may be transparent or may include an opening so that light can be detected by or emitted from an optical device on the substrate. The protective structure may be formed using a molding tool that provides the protective structure with grooves or may be molded around a hollow conductive structure to create grooves. An electrical component mounted to the fabric may be embedded within printed circuit layers.

A component carrier includes a stack with at least one electrically conductive layer structure, at least one electrically insulating layer structure, a cavity delimited at a bottom side at least partially by a top side of a stepped metal structure of the at least one electrically conductive layer structure, and a component embedded in the cavity and arranged on the stepped metal structure. A bottom side of the stepped metal structure has a flat surface extending continuously along at least one horizontal direction.

A method for manufacturing a flex inlay is provided. The method includes providing a flexible printed circuit having opposed surfaces. The method includes attaching components to a surface of the flexible printed circuit. The method includes applying a coverlay over at least one surface of the flexible printed circuit, wherein the coverlay is patterned to not cover any components attached to the surface of the flexible printed circuit. The coverlay at least in part forms an essentially planar surface of the flex inlay.

A packaging method includes steps of: forming first and second wiring layers electrically connected to each other on two opposite surfaces of a substrate; then configuring mother substrate interconnecting bumps on the first wiring layer and along perimeter of a daughter substrate unit, and then cutting along the perimeter of the daughter substrate unit to expose lateral faces of the mother substrate interconnecting bumps and configuring solder materials thereon; then configuring first and second chips on the first and the second wiring layers to form electrical interconnection between the two chips. A package structure enables interconnecting two chips through one single daughter substrate unit with its wiring layers directly connecting with lateral face contacts of the mother carrier substrate through the mother substrate interconnecting bumps. Hence, area of the daughter substrate unit is reduced; lengths of the interconnection paths are shortened, and qualities of communication and space utilization are enhanced.

Disclosed are a circuit board and its preparation method. The circuit board includes a base layer, a transmission wire layer including multiple conductor tabs, and an insulating and thermally conductive layer including multiple thermally conductive portions. A gap is defined between each adjacent two of the multiple conductor tabs to expose at least a portion of the base layer, and the gap is filled with a corresponding thermally conductive portion. A height of the thermally conductive portion is larger than heights of each adjacent two of the multiple conductor tabs to define a connection groove. The circuit board the disclosure providing enhances heat dissipation performance of circuit boards.