A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.

Patterns of homogenous, electroless-plated metals within and on one or both sides of a porous substrate (such as nanocellulose sheets) enable the formation of an matrix of metal within pores of the substrate that can connect patterns on both sides of the substrate. These can serve as circuits with applications in, for example, wearable electronics.

Aqueous dispersions of artificially synthesized, mussel-inspired polydopamine nanoparticles were inkjet printed on flexible polyethylene terephthalate (PET) substrates. Narrow line patterns (4 m in width) of polydopamine resulted due to evaporatively driven transport (coffee ring effect). The printed patterns were metallized via a site-selective Cu electroless plating process at a controlled temperature (30 C.) for varied bath times. The lowest electrical resistivity value of the plated Cu lines was about 6 times greater than the bulk resistivity of Cu. This process presents an industrially viable way to fabricate Cu conductive fine patterns for flexible electronics at low temperature, and low cost.

An input sensing unit includes a first metal pattern layer including a plurality of first conductive lines extending in a first direction. A first insulating layer is disposed on the first metal pattern layer. A second metal pattern layer is positioned above the first insulating layer and includes a plurality of second conductive lines extending in a second direction intersecting the first direction. A second insulating layer is disposed on the second metal pattern layer. A sensing electrode is disposed on the second insulating layer and is electrically connected to the second metal pattern layer through a contact hole defined in the second insulating layer. An anti-reflection pattern layer is disposed on the first and second metal pattern layers to overlap the first and second metal pattern layers along a direction orthogonal to an upper surface of the anti-reflection pattern layer.

A method for selective metallization includes: selectively adsorbing catalytic nanoparticles onto an imprint mold to form a selectively adsorbed catalytic nanoparticle (SACN) mold; using the SACN mold in an imprinting process to synchronously transfer a pattern and the catalytic nanoparticles onto a film; separating the film from the SACN mold; and selectively depositing metal onto the film based on the pattern transferred to the film.

Methods of patterning electroless metals on a substrate are presented. The substrate is covered by a blocking reagent. After formation of a catalyst blocking layer on the substrate, portions of the catalyst blocking layer are removed to form a circuit pattern. A catalyst is placed the surfaces of both the catalyst blocking layer and the exposed substrate. The catalyst blocking layer prevents or reduces catalytic activity of the catalyst. Electroless metal plating is performed to plate a metal at the active portions of the catalyst.

A multi-layer circuit board is formed multiple layers of a catalytic layer, each catalytic layer having an exclusion depth below a surface, where the cataltic particles are of sufficient density to provide electroless deposition in channels formed in the surface. A first catalytic layer has channels formed which are plated with electroless copper. Each subsequent catalytic layer is bonded or laminated to an underlying catalytic layer, a channel is formed which extends through the catalytic layer to an underlying electroless copper trace, and electroless copper is deposited into the channel to electrically connect with the underlying electroless copper trace. In this manner, traces may be formed which have a thickness greater than the thickness of a single catalytic layer.

A method for forming a circuit pattern on an integrated substrate structure includes providing an insulating surface which includes a pattern forming portion. An activation ink is deposited only on the pattern forming portion to form a non-conductive isolation layer. A first metal layer is formed on the non-conductive isolation layer by electroless plating. A patterned portion of the first metal layer is isolated from a remaining portion of the first metal layer to form the circuit pattern. A non-conductive masking layer is applied on the first metal layer. A second metal layer is formed on the non-conductive masking layer. A surface mount land pattern and pad configuration is determined. A solder mask layer is applied to the patterned portion. A protective layer is applied to protect pad areas not covered by the solder mask layer. An electrical component may then be mounted to the pad(s).

An input sensing unit includes a first metal pattern layer including a plurality of first conductive lines extending in a first direction. A first insulating layer is disposed on the first metal pattern layer. A second metal pattern layer is positioned above the first insulating layer and includes a plurality of second conductive lines extending in a second direction intersecting the first direction. A second insulating layer is disposed on the second metal pattern layer. A sensing electrode is disposed on the second insulating layer and is electrically connected to the second metal pattern layer through a contact hole defined in the second insulating layer. An anti-reflection pattern layer is disposed on the first and second metal pattern layers to overlap the first and second metal pattern layers along a direction orthogonal to an upper surface of the anti-reflection pattern layer.

Depicted embodiments are directed to an Application Specific Electronics Packaging (ASEP) system, which enables the manufacture of additional products using reel to reel (68a, 68b) manufacturing processes as opposed to the batch processes used to currently manufacture electronic products and MIDs. Through certain ASEP embodiments, it is possible to integrate connectors, sensors, LEDs, thermal management, antennas, RFID devices, microprocessors, memory, impedance control, and multi-layer functionality directly into a product.