A method for preparing a conductive circuit can begin with the preparation of a non-conductive substrate having a top surface and a bottom surface, and then utilizing a pulse laser to create a top circuit pattern upon the top surface, a bottom circuit pattern upon the bottom surface, and a through hole connecting the top circuit pattern with the bottom circuit pattern. Subsequently, a conductive circuit is formed upon the top circuit pattern and the bottom circuit pattern and inside the through hole, wherein the conductive circuit is restricted from being formed upon the top surface outside of the top isolation region and the bottom surface outside of the bottom isolation region.

A circuit assembly (200) is disclosed comprising a substrate (210) and conducting layers (250) on opposing sides of the substrate (210), there being at least one via (220) through the substrate (210), which via (220) forms a conductive path between the conducting layers, wherein the substrate (210) is a foam substrate, and wherein the via (220) is provided with a solid dielectric lining (270) plated with a conducting material (250).

On a glass substrate formed with a plurality of through holes, an electrode-portion forming step of forming an electrode portion in each of the through holes, a resin-material layer forming step of forming a resin-material layer on a topside of the glass substrate, a via-hole forming step of forming a via hole in a resin-material layer formed on the glass substrate at a location atop the electrode portion, a filling step of filling the via hole with a conductive elastic material, a semi-hardening step of semi-hardening the conductive elastic material, a separation step of separating the resin-material layer, an insulation-portion forming step of forming an insulation portion on the topside of the glass substrate by using an insulating elastic material, and a hardening step of hardening the insulation portion along with the conductive elastic material are performed.

A method for plating a printed circuit board, includes placing a substrate, including a through hole, in contact with a plating solution and disposing the substrate to face an electrode; and applying a pulsed current to each surface of the substrate, including applying pulsed currents of opposite polarity to both surfaces of the substrate at least once and applying pulsed forward currents to both surfaces of the substrate at least once, to plate from a middle to an end of the through hole.

A conductive network fabrication process is provided and includes filling a hole formed in a substrate with dielectric material, laminating films of the dielectric material on either side of the substrate, opening a through-hole through the dielectric material at the hole, depositing a conformal coating of dielectric material onto an interior surface of the through-hole and executing seed layer metallization onto the conformal coating in the through-hole to form a seed layer extending continuously along an entire length of the through-hole.

Disclosed are a method for fabricating a printed circuit board wherein through-holes are formed in an organic substrate, followed by forming micro-circuit patterns through sputtering and plating, whereby the printed circuit board has low permittivity properties and enables high-speed processing, and a printed circuit board fabricated thereby. The disclosed method for fabricating a printed circuit board comprises the steps of: preparing a base substrate; forming a through-hole perforating the base substrate; forming a thin seed layer on the base substrate and in the through-hole; forming a thin plate layer on the thin seed layer; and etching the thin seed layer and the thin plate layer to form a micro-circuit pattern, wherein the base substrate is one selected from an organic substrate, FR-4, and Prepreg.

The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A current introduction terminal includes a board made of resin. The board has a first face and a second face opposite each other. The board hermetically separates environments of different air pressures from each other. A plurality of through via holes corresponding both to a plurality of metal terminals of a first surface-mount connector to be mounted on the first face and to a plurality of metal terminals of a second surface-mount connector to be mounted on the second face are formed to penetrate between the first and second faces, and then hole parts of the through via holes are filled with resin.

A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. The catalytic laminate is subjected to a drilling and blanket surface plasma etch operation to expose the catalytic particles, followed by an electroless plating operation which deposits a thin layer of conductive material on the surface. A photo-masking step follows to define circuit traces, after which an electro-plating deposition occurs, followed by a resist strip operation and a quick etch to remove electroless copper which was previously covered by photoresist.