A process for making a circuit board from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth includes drilling holes, etching the surface to expose the catalytic particles, electroless plating the unmasked areas, applying a mask to the etched surface, electroplating the exposed areas using the electroless plating to form a continuous conductor, then stripping the mask and etching away the electroless copper deposition.

A glass core device with a wiring pattern on a first surface of a glass core and a wiring pattern on a second surface thereof being electrically connected via a wiring pattern embedded in TGVs formed in the glass core. In a state of being cut out by dicing, each glass core has a second surface and side faces which are continuously covered with an outer protective layer.

A circuit board includes a baseboard, a first conductive circuit layer, a second conductive circuit layer, at least one through hole, and a number of conductive lines. The first conductive circuit layer includes a number of first conductive circuit lines formed on a first side of the baseboard. The second conductive circuit layer includes a number of second conductive circuit lines formed on a second side of the baseboard. The through hole is defined through the first conductive circuit layer, the baseboard, and the second conductive circuit layer. The number of conductive lines are formed in an inner wall of the through hole and spaced apart around the through hole. Each conductive line electrically couples one of the first conductive circuit lines to a corresponding one of the second conductive circuit lines.

A technique for making a glass core substrate that is less prone to cracking. A core substrate of the present invention includes a glass plate and a first conductor pattern provided on a first main surface of the glass plate. The first conductor pattern includes a first nickel plating layer that is provided on the first main surface of the glass plate and has a phosphorus content of 5 mass % or less and a first copper plating layer that is provided on the first nickel plating layer.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A circuit assembly (200) is disclosed comprising a substrate (210) and conducting layers (250) on opposing sides of the substrate (210), there being at least one via (220) through the substrate (210), which via (220) forms a conductive path between the conducting layers, wherein the substrate (210) is a foam substrate, and wherein the via (220) is provided with a solid dielectric lining (270) plated with a conducting material (250).

Disclosed herein is a method of forming vias in electrical laminates comprising laminating a sheet having a layer comprising a crosslinkable polymer composition to a substrate wherein the crosslinkable polymer composition has a viscosity at lamination temperatures in the range of 200 Pa.Math.s to 100,000 Pa.Math.s, forming at least one via in the crosslinkable polymer layer by laser ablation; and after the forming of the at least one via, thermally curing the crosslinkable polymer layer. According to certain embodiments the cross linkable polymer composition has a viscosity at lamination temperature of at least 5000 Pa.Math.s. This method yields good lamination results, good via profiles, and good desmear results when such compositions are used and the via is laser ablated before cure.

A glass wiring board in which a glass substrate with a small thickness is used as a core substrate to prevent glass breakage during manufacture, and an analog splitter composed of a capacitor and an inductor is formed on the glass substrate so as to stabilize the electrical properties of the analog splitter. An inductor is formed using a through electrode which is in contact with an inorganic adhesive layer on a glass substrate on which the inorganic adhesive layer is formed. A capacitor is formed using an insulating resin opening part formed in an insulating resin layer covering the glass substrate having wiring. The inductor and the capacitor are formed on different layers.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.