A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).

A flexible multilayer construction (1000) for mounting a plurality of light emitting semiconductor devices (LESDs 100, 110, 120) includes a flexible dielectric substrate (200) comprising top (210) and bottom (220) major surfaces, and pluralities of corresponding electrically conductive top (300, 310, 320, 330) and bottom (500, 510, 520, 530) pads disposed on the top and bottom major surfaces, respectively. An electrically conductive via (400, 410, 420, 430) connects each pair of corresponding top and bottom pads, a side of each top pad partially overlapping a side of the corresponding bottom pad and a side of the substrate, such that in a plan view, each top pad fully overlaps the corresponding bottom pad.

The present disclosure provides a printed circuit board including a plurality of conductive layers separated by insulating medium and a plurality of connection structures. Each connection structure penetrates each of the conductive layers. The plurality of conductive layers comprises a first conductive layer in which first signal lines are located and a second conductive layer in which second signal lines are located, and the first and second signal lines are connected via the connection structures. Anti-pads surrounding the connection structures are provided on others of the plurality of conductive layers except the first and the second conductive layers. For a same connection structure, the anti-pads surrounding the connection structure include adjacent anti-pads and nonadjacent anti-pads. Size of the adjacent anti-pads in any direction parallel to the conductive layers is smaller than that of the nonadjacent anti-pads. The present disclosure also provides a display apparatus.

A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).

A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

The present disclosure provides a printed circuit board including a plurality of conductive layers separated by insulating medium and a plurality of connection structures. Each connection structure penetrates each of the conductive layers. The plurality of conductive layers comprises a first conductive layer in which first signal lines are located and a second conductive layer in which second signal lines are located, and the first and second signal lines are connected via the connection structures. Anti-pads surrounding the connection structures are provided on others of the plurality of conductive layers except the first and the second conductive layers. For a same connection structure, the anti-pads surrounding the connection structure include adjacent anti-pads and nonadjacent anti-pads. Size of the adjacent anti-pads in any direction parallel to the conductive layers is smaller than that of the nonadjacent anti-pads. The present disclosure also provides a display apparatus.

A circuit substrate includes a dielectric layer, a first conductive structure and a second conductive structure. The first conductive structure includes a first conductive circuit and a first conductive via. The first conductive circuit is disposed on the dielectric layer. The first conductive via is disposed in the dielectric layer, and the first conductive circuit is connected to the first conductive via. The second conductive structure includes a second conductive circuit and a second conductive via. The second conductive circuit is disposed in the dielectric layer, the second conductive circuit and the first conductive circuit of the first conductive structure are arranged with an interval, and the second conductive via surrounds the first conductive via with an interval. The second conductive structure has an extending portion. The extending portion protrudes toward the first conductive via and does not contact the first conductive via.

A power signal transmission structure and a design method are provided. The power supply signal transmission structure is adapted for a circuit board having a first surface and a second surface opposite to the first surface, and the power signal transmission structure includes a first power electrode, a second power electrode, and a plurality of vias. The first power electrode is disposed on the first surface and has a plurality of power pad regions for receiving a power signal. The second power electrode is disposed on the second surface. The vias penetrate the circuit board to electrically connect the first power electrode and the second power electrode. The vias are arranged in accordance with the current direction of the power signal to balance the current received by the vias.

A flexible multilayer construction (1000) for mounting a plurality of light emitting semiconductor devices (LESDs 100, 110, 120) includes a flexible dielectric substrate (200) comprising top (210) and bottom (220) major surfaces, and pluralities of corresponding electrically conductive top (300, 310, 320, 330) and bottom (500, 510, 520, 530) pads disposed on the top and bottom major surfaces, respectively. An electrically conductive via (400, 410, 420, 430) connects each pair of corresponding top and bottom pads, a side of each top pad partially overlapping a side of the corresponding bottom pad and a side of the substrate, such that in a plan view, each top pad fully overlaps the corresponding bottom pad.

A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.