Provided is a circuit module including a power supply chip module, a load chip module, and a system board. A power supply output terminal group of the power supply chip module is arranged side by side in a row along a side of the power supply chip module board, the power supply input terminal group of a load chip module includes a specific terminal group arranged in a specific row that is a row along a side of the load chip module board, and a wiring width along an arrangement direction of the power supply output terminal group of a wiring pattern in which the power supply output terminal group is connected to the system board is equal to or more than a wiring width W31 along an arrangement direction of the specific terminal group of the wiring pattern in which the specific terminal group is connected to the system board.

A signal transmission method is applied to a receiving terminal so as to improve the anti-interference capability of the signals on the transmission line, and the signal transmission method includes: receiving a signal sent by a transmitting terminal through a transmission line; detecting whether there is a transmission error in the received signal; and when there is a transmission error in the received signal, adjusting at least one parameter of specified parameters affecting an anti-interference capability of signals on the transmission line, and/or controlling the transmitting terminal to adjust the at least one parameter of the specified parameters affecting the anti-interference capability of signals on the transmission line.

An embodiment of a printed circuit board includes a first insulating layer, a metal layer disposed above the first insulating layer, a second insulating layer disposed above the metal layer, and signal lines disposed above the second insulating layer, the signal lines extending in a first direction and having line widths in a second direction perpendicular to the first direction. The metal layer has open areas overlapping the signal lines in a third direction perpendicular to the first and second directions. In another embodiment, the open areas are replaced with metal meshes.

A flexible printed circuit board includes: a base film; a first circuit pattern disposed on an upper surface of the base film; a second circuit pattern disposed on a lower surface of the base film; and a boundary reinforcing pattern expanding the first circuit pattern in a width direction of the first circuit pattern based on a virtual boundary along which the first circuit pattern and the second circuit pattern meet each other in an overlay of the first circuit pattern and the second circuit pattern.

An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

A circuit board with integrated fusing includes an insulating substrate having a circuit trace formed on a surface thereof, the circuit trace including a first circuit trace portion and a second circuit trace portion. A fusible link electrically connects the first circuit trace portion to the second circuit trace portion, the fusible link including a planar surface extending from the first circuit trace portion to the second circuit trace portion. A dielectric reflow encapsulates the fusible link on the planar surface from the first circuit trace portion to the second circuit trace portion.

Electrical conductors are disclosed. More particularly, undulating electrical conductors are disclosed. Certain disclosed electrical conductors may be suitable to be disposed on flexible or stretchable substrates.

A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.

A flip chip interconnection including a circuit board is disclosed. The circuit board includes a substrate, inner leads, a T-shaped circuit line and a dummy pattern. The inner leads, the T-shaped circuit line and the dummy pattern are located on an inner bonding area of the substrate. The T-shaped circuit line includes a main segment, a branch segment and a connection segment that is connected to the main segment and the branch segment. The main segment and the branch segment are extended along a lateral direction and a longitudinal direction, respectively. The dummy pattern is located between the connection segment and the inner leads.

Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.