A package carrier includes a plurality of first circuit patterns, a plurality of second circuit patterns and an insulating material layer. The second circuit patterns are disposed between any two the first circuit patterns and are directly connected to the first circuit patterns. In a cross-sectional view, a first thickness of each of the first circuit patterns is greater than a second thickness of each of the second circuit patterns. A first surface of each of the first circuit patterns is aligned with a second surface of each of the second circuit patterns. The insulating material layer at least contacts the first circuit patterns.

A resin multilayer board includes a substrate including a stack of resin layers, and a first metal pin including a first end portion exposed at a first main surface of the substrate and penetrating through at least one of the resin layers in a thickness direction, wherein a gap is provided at a portion of an interface between a lateral side of the first metal pin and the resin layer.

A printed wiring board used to suppress parasitic component is provided. The printed wiring board 100 includes a multi-layer substrate 110, and a power line 50 laid on the multi-layer substrate 110 and connected with a power terminal row T11a-T11d of a semiconductor device 10. The power line 50 includes a first wiring pattern 51 formed on a surface of the multi-layer substrate 110, a second wiring pattern 52 formed within the multi-layer substrate 110, and interlayer connections 53x and 53y electrically conducting the first wiring pattern 51 and the second wiring pattern 52 to bypass at least a portion of the power terminal row T11a-T11d.

A printed circuit board includes: an insulating layer having a via hole formed therein; a single layer metal pad disposed in the insulating layer and having a center portion that is exposed by the via hole, the center portion of the pad having a higher roughness than peripheral portions of the pad; and a via formed in the via hole and connected to the center portion of the pad.

The present disclosure provides a panel, a manufacturing method for the same, and a terminal. The panel includes: a base substrate; at least one differential signal line group on the base substrate, each including two signal lines; and at least one ground wire group on the base substrate and on the same side of the base substrate as the at least one differential signal line group. The at least one ground wire group is in one-to-one correspondence with the at least one differential signal line group, each ground wire group includes two ground wires, and orthographic projections of the two ground wires in each ground wire group on the base substrate are on two sides of an orthographic projection of a corresponding differential signal line group on the base substrate, respectively.

A manufacturing method for a circuit board and a circuit board are provided. The method includes steps: providing a substrate having a first metal layer; forming a patterned first opening on the first metal layer to expose the substrate; forming a patterned first dielectric layer on the substrate, the first dielectric layer is made of a photosensitive dielectric material and covers the first opening; photosensitizing the first dielectric layer to cure the first dielectric layer; forming a patterned second metal layer on the first metal layer; forming a patterned third metal layer on the second metal layer, and the third metal layer being adjacent to the first dielectric layer; removing a portion of the first metal layer not covered by the second metal layer; and forming a second dielectric layer on the substrate. A thickness of the third metal layer is greater than a thickness of the second metal layer.

A signal transmission method is applied to a receiving terminal so as to improve the anti-interference capability of the signals on the transmission line, and the signal transmission method includes: receiving a signal sent by a transmitting terminal through a transmission line; detecting whether there is a transmission error in the received signal; and when there is a transmission error in the received signal, adjusting at least one parameter of specified parameters affecting an anti-interference capability of signals on the transmission line, and/or controlling the transmitting terminal to adjust the at least one parameter of the specified parameters affecting the anti-interference capability of signals on the transmission line.

A resin multilayer board includes a substrate including a stack of resin layers, and a first metal pin including a first end portion exposed at a first main surface of the substrate and penetrating through at least one of the resin layers in a thickness direction, wherein a gap is provided at a portion of an interface between a lateral side of the first metal pin and the resin layer.

A package carrier includes a plurality of first circuit patterns, a plurality of second circuit patterns and an insulating material layer. The second circuit patterns are disposed between any two the first circuit patterns and are directly connected to the first circuit patterns. In a cross-sectional view, a first thickness of each of the first circuit patterns is greater than a second thickness of each of the second circuit patterns. A first surface of each of the first circuit patterns is aligned with a second surface of each of the second circuit patterns. The insulating material layer at least contacts the first circuit patterns.

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, at least one first electrically conductive track extending from a vertical level defined by one of the layer structures up to a first height, at least one second electrically conductive track extending from the vertical level defined by the one of the layer structures up to a second height being larger than the first height, and at least one further electrically insulating layer structure in which the at least one first electrically conductive track and the at least one second electrically conductive track are embedded.