A connector for electrically connecting to conductive structures formed on a semiconductor device includes a core including an isolation layer and signal vias and ground vias formed in the isolation layer; a first ground plane formed on a surface of the core and electrically connected to the ground vias; a first set of contact elements formed on a first surface of the core and electrically connected to the signal vias to form signal pins; a second set of contact elements formed on the first surface and electrically connected to a subset of the ground vias to form ground pins. The remaining ground vias without contact elements form buried ground vias. The first and second sets of contact elements are arranged on the first surface of the core to surround each signal pin by at least one adjacent ground pin and one or more adjacent buried ground vias.

An electronic assembly includes an electronic package having an integrated circuit component and interposer assemblies with compressible interposer contacts electrically connected thereto. Cable connector modules are coupled to the interposer assemblies. A cover assembly is coupled to the upper surface of the electronic package over the cable connector modules. The cover assembly includes bridge assemblies having plates in a plate stack that are independently movable. A load plate engages upper edges of the plates of the bridge assemblies and press against the plates to drive the bridge assemblies into the cable connector modules using compression hardware. The cable connector modules compress the interposer contacts of the interposer assemblies when the load plate presses the plates of the bridge assemblies into the cable connector modules.

Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

A semiconductor device, including a semiconductor module, a positioning member and a printed board. The semiconductor module includes a case that stores a semiconductor chip, a plurality of external terminals electrically connected to the semiconductor chip and extending upward from a front surface of the case, and a reference pin extending upward from the front surface of the case. The positioning member has a reference hole and a plurality of supporting holes penetrating therethrough. The printed board including a plurality of terminal holes that respectively correspond to the plurality of external terminals. The printed board is disposed on the front surface of the case via the positioning member. The plurality of external terminals of the semiconductor module are respectively attached to the plurality of terminal holes.

A pluggable processor module includes a microprocessor package, a voltage regulator including a capacitor board, and contact pads that each include a first side in contact with the microprocessor package and a second side in contact with the capacitor board.

An electronic-component carrier board includes carrier plates formed in a stack, and insulating layers each disposed between two adjacent ones of the carrier plates. Multiple conductive pins extend through the insulating layers and the carrier plates. Multiple conductive wires equal in length and width are provided. Each conductive wire is connected to one of the conductive pins, covered by one of the insulating layers, disposed between two adjacent ones of the carrier plates, and extends outwardly from the stack of the carrier plates. A wiring method for the electronic-component carrier board is also disclosed.

Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.

A circuit system includes an integrated circuit package mounted on a first side of a printed circuit board and a power regulator connected to power terminals of the integrated circuit package through a cutout in the printed circuit board. The power regulator draws power from the printed circuit board by way of connections on a shelf region extending beyond an area of the cutout.

In one embodiment, a package substrate or main circuit board includes electrical connectors arranged in a compressed array pattern, wherein a distance between a connector and its neighboring connectors in a direction of compression is less than a distance between the connector and its neighboring connectors in other directions. The array pattern may be hexagonal or rectangular, and differential pairs of the electrical connectors may be arranged in the direction of compression.

A probe card device includes a probe head including a plurality of pins, wherein each of the pins includes a body, a first metal layer formed on the body, and a second metal layer covering the first metal layer; a multi-layered flexible board electrically connected to the pins; a support plate, the multi-layered flexible board disposed on a first surface of the support plate; and a circuit board electrically connected to the multi-layered flexible board.