A memory device according to an embodiment includes a fluid layer extending in a first direction, a particle in the fluid layer, a first control electrode made of a first material, a first insulating film provided between the fluid layer and the first control electrode, a second control electrode made of a second material and provided to be spaced apart from the first control electrode in the first direction, a second insulating film provided between the fluid layer and the second control electrode, a third control electrode made of a third material different from the first material and the second material and provided between the first control electrode and the second control electrode, and a third insulating film provided between the fluid layer and the third control electrode.

A method of making flexible and stretchable semiconductor devices with reduced footprints can include coating a gate electrode layer having a first composition over an elastomer layer, solidifying a portion of the gate electrode layer by irradiation to form a gate electrode, coating a dielectric layer having a second composition over the gate electrode layer, solidifying a portion of the dielectric layer by the irradiation to form a gate dielectric, coating a semiconductor layer having a third composition over the dielectric layer, solidifying a portion of the semiconductor layer by the irradiation to form a device core, coating a terminal layer having the first composition over the dielectric layer, and solidifying a portion of the terminal layer by the irradiation to form a source electrode and a drain electrode contacting the semiconductor layer.

A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Printable and stretchable thin-film devices and fabrication techniques are provided for forming fully-printed, intrinsically stretchable thin-film transistors and integrated logic circuits using stretchable elastomer substrates such as polydimethylsiloxane (PDMS), semiconducting carbon nanotube network as channel, unsorted carbon nanotube network as source/drain/gate electrodes, and BaTiO.sub.3/PDMS composite as gate dielectric. Printable stretchable dielectric layer ink may be formed by mixing barium titanate nanoparticle (BaTiO.sub.3) with PDMS using 4-methyl-2-pentanone as solvent.

In a method, a charged metal dot is deposited on a first position of a surface of a semiconductor substrate. Then, a charged region is formed on a second position of the surface of the semiconductor substrate, thereby establishing of which an electric field direction from the first position toward the second position. The first position is spaced apart from the second position by a distance. Thereafter, a precursor gas flows along the electric field direction on the semiconductor substrate, thereby forming a carbon nanotube (CNT) on the semiconductor substrate.

An object is to provide a field effect transistor using a metal organic framework film as a semiconductor layer and having a novel structure. This embodiment is a field effect transistor that includes a substrate, a source electrode, a drain electrode, a gate electrode, and a metal organic framework film as a semiconductor layer. The metal organic framework film has a stacked structure. A plurality of crystalline structures in which organic ligands having a π-conjugated skeleton and metal ions are coordinated to be developed in a planar direction of the substrate are stacked on the substrate via a π-π interaction in the stacked structure. The crystalline structures each have pores formed by the coordination of the organic ligands and the metal ions. The pores in the adjacent crystalline structures communicate with one another in a film thickness direction in the stacked structure. The field effect transistor is a top-contact type.

A transistor device (10) is disclosed comprising a source electrode (14) a drain electrode (12) and an enzyme (31) for facilitating generation of a charge carrier from an analyte. The transistor device also comprises a polymer layer (30) for retaining the enzyme (31), the polymer layer (30) being conductive to the charge carrier. The device also comprises an ohmic conductor (32) in contact with said polymer layer (30) for applying a gate voltage to said polymer layer (30). The device also comprises an organic semiconducting layer (18) connecting the source electrode (14) to the drain electrode (12). Also disclosed is a method of making and using the device (10).

The present invention relates to organic thin film sensors and the preparation and use thereof in sensing applications, and in particular in glucose sensing. The sensor is characterised by a layered structure comprising a porous wicking layer whose surface is configured to receive a liquid sample. An enzyme is disposed on or within the porous layer for facilitating the generation of a charge carrier from an analyte. A polymer layer in contact with the porous layer is connected to an ohmic conductor for applying a gate voltage to the polymer layer, the polymer layer being conductive to the charge carrier; and an organic semiconducting layer is connected to a source electrode and a drain electrode.

The present disclosure provides a method for manufacturing an array substrate, an array substrate, and a display device. The method for manufacturing the array substrate includes: forming a light-shielding layer and a buffer layer in sequence on a base substrate; forming an active layer on the buffer layer, and forming a first via hole in the active layer; forming an interlayer dielectric layer on the active layer; forming a second via hole in the interlayer dielectric layer at a position corresponding to the first via hole and a third via hole in the buffer layer at a position corresponding to the first via hole by a single patterning process; forming a source/drain electrode layer on the interlayer dielectric layer, in which the source/drain electrode layer is electrically connected to the light-shielding layer through the second via hole, the first via hole and the third via hole in sequence.

In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.