A manufacturing method of a semiconductor memory device in an embodiment, includes: forming a first mask pattern having a first opening and a plurality of second openings above a stacked body; forming a second mask pattern covering some of the plurality of second openings; and etching the stacked body with the first mask pattern as a mask while sequentially exposing the plurality of second openings by causing an end of the second mask pattern to retreat to form a first hole extending in the stacked body in a stacking direction of the stacked body at a position of the first opening and form a plurality of second holes extending in the stacked body to different depths in the stacking direction at positions of the plurality of second openings, and reaching first layers of a plurality of first layers at different levels.

Methods and structures corresponding to superconducting apparatus including superconducting layers and traces are provided. A method for forming a superconducting apparatus includes forming a first dielectric layer on a substrate by depositing a first dielectric material on the substrate and curing the first dielectric material at a first temperature. The method further includes forming a first superconducting layer comprising a first set of patterned superconducting traces on the first dielectric layer. The method further includes forming a second dielectric layer on the first superconducting layer by depositing a second dielectric material on the first superconducting layer and curing the second dielectric material at a second temperature, where the second temperature is lower than the first temperature. The method further includes forming a second superconducting layer comprising a second set of patterned superconducting traces on the second dielectric layer.

A method for fabricating a second generation high-temperature superconductor (2G-HTS) tape, including: (S1) depositing a superconducting thin film on a surface of a ductile metal substrate with a buffer layer; (S2) forming a micro-holes array pattern on a surface of the superconducting thin film by etching using a reel-to-reel dynamic femtosecond infrared laser etching system, where the micro-holes array pattern covers the superconducting thin film; (S3) depositing a superconducting thick film on the surface of the superconducting thin film; and (S4) depositing a silver protective layer and a copper stabilization layer on a surface of the superconducting thick film.

A 2nd generation high temperature superconductor wire that prevents mechanical destruction from the wire edge due to slitting. A 2G HTS wire according to embodiments of the present invention has a structure that prevents mechanical destruction from the wire edge. This can be accomplished by forming a striation at or near the edge of the wire where the buffer and superconducting layers are removed to prevent any propagation of edge cracks from damaging the HTS wire.

A method includes providing a film of a high-temperature superconductor compound on a flexible substrate, where a portion of the film has a first oxygen state, and exposing a portion of the film to a focused ion beam to create a structure within the film. The structure may result from the portion of the film being partially or completely removed. The structure may be a trench along the length or width of the film. The method may include annealing the exposed portion of the film to a second oxygen state. The oxygen content of the second oxygen state may be greater or less than the oxygen content of the first oxygen state.

A manufacturing method of a semiconductor memory device in an embodiment, includes: forming a first mask pattern having a first opening and a plurality of second openings above a stacked body; forming a second mask pattern covering some of the plurality of second openings; and etching the stacked body with the first mask pattern as a mask while sequentially exposing the plurality of second openings by causing an end of the second mask pattern to retreat to form a first hole extending in the stacked body in a stacking direction of the stacked body at a position of the first opening and form a plurality of second holes extending in the stacked body to different depths in the stacking direction at positions of the plurality of second openings, and reaching first layers of a plurality of first layers at different levels.

Techniques for forming quantum circuits, including connections between components of quantum circuits, are presented. A trench can be formed in a dielectric material, by removing a portion of the dielectric material and a portion of conductive material layered on top of the dielectric material, to enable creation of circuit components of a circuit. The trench can define a regular nub or compensated nub to facilitate creating electrical leads connected to the circuit components on a nub. The compensated nub can comprise recessed regions to facilitate depositing material during evaporation to form the leads. For compensated nub implementation, material can be evaporated in two directions, with oxidation performed in between such evaporations, to contact leads and form a Josephson junction. For regular nub implementation, material can be evaporated in four directions, with oxidation performed in between the third and fourth evaporations, to contact leads and form a Josephson junction.

A solid state cooler device is disclosed that includes a first superconductor shunt, a first normal metal pad disposed on the first superconductor shunt, and a first insulator layer and a second insulator layer disposed on the normal metal pad and separated from one another by a gap. The solid state cooler device also includes a first superconductor pad disposed on the first insulator layer and a second superconductor pad disposed on the second insulator layer, a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad. Hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad, wherein the first superconductor shunt facilitates even current distribution through the device.

The present invention relates to a superconducting nanowire single-photon detector, which can include a superconducting nanowire configured and arranged for the incidence of a photon on a region thereof and the formation, on that region, of a localized non-superconducting region or hotspot.

The superconducting nanowire is made of a high-Tc cuprate superconductor material having a superconducting critical temperature above 77 K.

The present invention also relates to a method for obtaining the superconducting nanowire single-photon detector of the present invention.

Techniques for forming quantum circuits, including connections between components of quantum circuits, are presented. A trench can be formed in a dielectric material, by removing a portion of the dielectric material and a portion of conductive material layered on top of the dielectric material, to enable creation of circuit components of a circuit. The trench can define a regular nub or compensated nub to facilitate creating electrical leads connected to the circuit components on a nub. The compensated nub can comprise recessed regions to facilitate depositing material during evaporation to form the leads. For compensated nub implementation, material can be evaporated in two directions, with oxidation performed in between such evaporations, to contact leads and form a Josephson junction. For regular nub implementation, material can be evaporated in four directions, with oxidation performed in between the third and fourth evaporations, to contact leads and form a Josephson junction.