A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

A memory structure is provided. The memory structure includes a top terminal, a multi-level nonvolatile electrochemical cell, a bottom terminal, a pedestal contact in the same metal level as the bottom terminal, and a vertical conductor fully self-aligned to the multi-level nonvolatile electrochemical cell and extending vertically from the pedestal contact.

A resistive random access memory device is provided. The resistive random access memory device includes a first electrode, a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. One of the first electrode and the second electrode includes an ion supply layer providing two or more kinds of metal ions to the electrolyte layer. The two or more kinds of metal ions have different mobilities in the electrolyte layer. Two or more conductive bridges are generated by the two or more kinds of metal ions, respectively.

A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.

A semiconductor structure comprises a conductive bridge random access memory device and an access device connected in series with the conductive bridge random access memory device. The conductive bridge random access memory device and the access device are arranged in a vertical stack. The vertical stack has a sidewall profile that increases in width from a bottom surface of the vertical stack to a top surface of the vertical stack.

A memory device including a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.

A method of manufacturing a switching element includes forming a first electrode layer over a substrate, forming a switching structure on the first electrode layer, and forming a second electrode layer on the switching structure. The switching structure includes a plurality of unit switching layers that includes a first unit switching layer and a second unit switching layer. Forming the first unit switching layer includes forming a first unit insulation layer, and injecting first dopants into the first unit insulation layer by performing a first ion implantation process. Forming the second unit switching layer includes forming a second unit insulation layer, and injecting second dopants into the second unit insulation layer by performing a second implantation process.

A material belonging to the family of centrosymmetric Mott insulators is used as an active material in a resistively switched memory for storing data. The material is placed between two electrical electrodes, by virtue of which an electric field of a preset value is applied in order to form, by way of an electron avalanche effect, an elementary information cell that has at least two logic states.

A phase change memory (PCM) device is provided. The PCM device includes a bottom electrode formed on a substrate, a heater electrode formed on the bottom electrode, the heater electrode having a tapered portion that becomes narrower in a direction away from the substrate. The PCM device also includes an interlayer dielectric (ILD) layer formed on the tapered portion of the heater electrode, the interlayer layer dielectric including an airgap that at least partially surrounds the tapered portion of the heater electrode. The PCM device also includes a phase change layer formed on the heater electrode, and a top electrode formed on the phase change layer.

The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M.sub.8XY.sub.6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M.sub.8XY.sub.6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell. It may not depend on a gated transistor and a diode, but relies on a non-linear variation characteristic of resistance of its own varied with voltage to achieve a self-gated function, which has a simple structure, easy integration, high density and low cost, capable of suppressing a reading crosstalk phenomenon in a cross array structure; and is also adapted for a planar stacked cross array structure and a vertical cross array structure, achieving 3D storage with a high density.