A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell.

A semiconductor memory device includes a substrate and a transistor disposed on the substrate. The transistor includes a source doped region, a drain doped region, a channel region, and a gate over the channel region. A data storage region is in proximity to the transistor and recessed into the substrate. The data storage region includes a ridge and a V-shaped groove. A bottom electrode layer conformally covers the ridge and V-shaped groove within the data storage region. A resistive-switching layer conformally covers the bottom electrode layer. A top electrode layer covers the resistive-switching layer.

A filament type non-volatile memory device, includes a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being suitable for having: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, the filament having a low electric resistance, and a highly resistive state, in which the filament is broken, the filament having a high electric resistance. The device further includes a shunt resistance electrically connected in parallel to the active layer, between the first electrode and the second electrode.

A semiconductor device includes a substrate, a first bit line disposed on the substrate, a first tunnel insulation layer disposed on the first bit line, a variable resistance structure disposed on the first tunnel insulation layer and having a pillar structure, a second tunnel insulation layer disposed on an upper surface of the variable resistance structure, a second bit line disposed on the second tunnel insulation layer, a barrier insulation layer disposed on a sidewall surface of the variable resistance structure, and a word line disposed on the barrier insulation layer. A dielectric constant of the barrier insulation layer is greater than a dielectric constant of each of the first and second tunnel insulation layers.

Provided are a resistive random access memory (RRAM) and a manufacturing method thereof. The resistive random access memory includes multiple unit structures disposed on a substrate. Each of the unit structures includes a first electrode, a first metal oxide layer, and a spacer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. The spacer is disposed on sidewalls of the first electrode and the first metal oxide layer. In addition, the resistive random access memory includes a second metal oxide layer and a second electrode. The second metal oxide layer is disposed on the unit structures and is connected to the unit structures. The second electrode is disposed on the second metal oxide layer.

The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.

A resistive random access memory (RRAM) and a method for operating the RRAM are disclosed. The RRAM includes at least two successively stacked conductive layers and a resistive switching layer situated between every adjacent two conductive layers, wherein a migration interface with an interface effect is formed at each interface between one conductive layer and the resistive switching layer in contact therewith, wherein the migration interface regulates, by the interface effect, vacancies formed in the resistive switching layer under the effect of an electrical signal. The regulation includes at least one of absorption, migration and diffusion.

A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.