H01L21/02063

INTERCONNECT STRUCTURE WITH HYBRID BARRIER LAYER
20220415798 · 2022-12-29 ·

The present disclosure relates to an integrated chip including a lower conductive wire within a first dielectric layer over a substrate. A second dielectric layer is over the first dielectric layer. A conductive via is over the lower conductive wire and within the second dielectric layer. A conductive liner layer lines sidewalls of the via. A barrier layer lines sidewalls of the conductive liner layer and lines sidewalls of the second dielectric layer. The conductive liner layer is laterally separated from the second dielectric layer by the barrier layer. The conductive liner layer vertically extends between sidewalls of the barrier layer from a bottom surface of the conductive via to a top surface of the lower conductive wire.

Methods of forming contact features in semiconductor devices

A semiconductor structure includes an isolation feature disposed over a semiconductor substrate, a semiconductor fin disposed over the semiconductor substrate and adjacent to the isolation feature, a source/drain (S/D) feature disposed over the semiconductor substrate and apart from the isolation feature, an interlayer dielectric (ILD) layer disposed over the isolation feature and the S/D feature, a first contact plug disposed in the ILD layer and over the isolation feature, a second contact plug disposed in the ILD layer and over the S/D feature, and a dielectric layer between surfaces of the first contact plug and the ILD layer and between a sidewall of the second contact plug and the ILD layer, where a bottom surface of the second contact plug is free of the dielectric layer.

CLEANING METHOD AND PLASMA PROCESSING APPARATUS

A substrate cleaning method includes: providing a substrate including a low-k layer containing silicon to a substrate support; etching the low-k layer by a plasma generated from a first gas; separating the etched substrate from the substrate support; and removing a reaction product attached to the substrate in the etching by a plasma generated from a second gas. The second gas includes a first carbon-containing gas represented by C.sub.xH.sub.yF.sub.z (y≥0, x/z>¼).

3D NAND etch

Methods of etching film stacks to form gaps of uniform width are described. A film stack is etched through a hardmask. A conformal liner is deposited in the gap. The bottom of the liner is removed. The film stack is selectively etched relative to the liner. The liner is removed. The method may be repeated to a predetermined depth.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.

Method for manufacturing semiconductor structure
11594540 · 2023-02-28 · ·

The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a bit line structure on a top surface of the substrate; forming a spacer structure on the bit line structure, the spacer structure including a sacrificial layer sandwiched by a first dielectric layer and a second dielectric layer; removing the sacrificial layer to form a gap between the first dielectric layer and the second dielectric layer; reducing a width of the gap; and forming a seal layer to seal the gap.

Chemical solution and method for treating substrate

The present invention provides a chemical solution which has an excellent dissolving ability for a transition metal-containing substance and can realize excellent smoothness of a portion to be treated. Furthermore, the present invention provides a method of treating a substrate. The chemical solution according to an embodiment of the present invention is used for removing a transition metal-containing substance on a substrate. The chemical solution contains one or more kinds of specific hypochlorous acids selected from the group consisting of hypochlorous acid and a salt thereof and contains one or more kinds of specific anions selected from the group consisting of ClO.sub.3.sup.− and Cl.sup.−. In a case where the chemical solution contains one kind of the specific anion, the content of one kind of the specific anion is 5 ppb by mass to 1% by mass with respect to a total mass of the chemical solution. In a case where the chemical solution contains two kinds of the specific anions, a content of each of two kinds of the specific anions is equal to or lower than 1% by mass with respect to the total mass of the chemical solution, and a content of at least one of two kinds of the specific anions is equal to or higher than 5 ppb by mass with respect to the total mass of the chemical solution.

METHOD FOR RESOLVING DEFECT OF SURFACE STRUCTURE OF TRENCH AND METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE
20230055868 · 2023-02-23 ·

The embodiments of the present disclosure propose a method for resolving a defect of surface structures of trenches and a method for preparing a semiconductor structure. The method for resolving a defect of surface structures of trenches includes: cleaning the trenches on a base with a cleaning liquid after the trenches are formed on the base, where the cleaning liquid is water.

SEMICONDUCTOR DEVICE WITH STACKED DIES AND METHOD FOR FABRICATING THE SAME
20220367415 · 2022-11-17 ·

The present application discloses a semiconductor device with stacked dies and the method for fabricating the semiconductor device with the stacked dies. The semiconductor device includes a first semiconductor die including a first substrate including a first and a second region, a first circuit layer on the first substrate, a control circuit on the first region and in the first circuit layer; and through die vias along the first circuit layer and the second region; a second semiconductor die stacked on the first semiconductor die and including second conductive pads connected to the through die vias and the control circuit; and a third semiconductor die stacked under the first semiconductor die and including third conductive pads connected to the through die vias and the control circuit. The through die vias, the second conductive pads, and the third conductive pads configure transmission channels through which the control circuit is capable to access the second and the third semiconductor die.

Etching solution for tungsten word line recess

Described herein is an etching solution suitable for both tungsten-containing metals and TiN-containing materials, which comprises: water; and one or more than one oxidizers; and one or more than one of the components selected from the group consisting of: one or more fluorine-containing-etching compounds, one or more organic solvents, one or more chelating agents, one or more corrosion inhibitors and one or more surfactants.