Provided is a treatment liquid for a semiconductor with ruthenium including a ligand which coordinates to ruthenium, the treatment liquid is a treatment liquid for inhibiting a ruthenium-containing gas generated when contacting a semiconductor wafer including ruthenium with the treatment liquid in a semiconductor forming process. Also provided is an inhibitor for the generation of a ruthenium-containing gas, including a compound having a carbonyl group or a heterocyclic compound. Further provided is a treatment agent for a ruthenium-containing waste liquid, including a compound having a carbonyl group or a heterocyclic compound.

A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures includes a substrate and a superconducting trace. Additionally, each of the semiconductor structures includes a passivation layer and one or more under bump metal (UBM) structures. The cryogenic electronic package also includes one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two superconducting semiconductor structures. The interconnect structures are electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures. A method of fabricating a cryogenic electronic package is also provided.

A semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over a substrate, and the gate structure includes a gate dielectric layer and a gate electrode layer. The semiconductor device structure includes an insulating capping layer formed over the gate electrode layer, and the insulating capping layer covers a top surface of the gate dielectric layer. The semiconductor device structure also includes a conductive via structure formed through the insulating capping layer, and a portion of the conductive via structure is lower than a top surface of the gate dielectric layer.

Semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a representative semiconductor device includes a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less, and a group III-V material over the group III material.

A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

A manufacturing method of a through substrate via includes at least the following steps. A protective liner is formed within an opening of a dielectric layer, where the opening exposes a portion of a semiconductor substrate underlying the dielectric layer. The portion of the semiconductor substrate is removed through the opening, where an overhang portion is formed at a top edge of the semiconductor substrate and masked by the protective liner after the removing. The overhang portion of the semiconductor substrate, the protective liner, and a portion of the dielectric layer adjoining the protective liner is removed to form a via hole. A conductive material is formed in the via hole.

According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.

Methods for selectively depositing a self-assembled monolayer (SAM) on metallic surfaces are disclosed. Some embodiments of the disclosure utilize phenanthroline or a phenanthroline derivative to form the self-assembled monolayer. Some embodiments selective form the self-assembled monolayer on tungsten or molybdenum. Some embodiments utilize the self-assembled monolayer to selectively deposit on dielectric surfaces over metallic surfaces.

This disclosure relates to a cleaning composition that contains 1) at least one chelating agent, the chelating agent being a polyaminopolycarboxylic acid; 2) at least one organic solvent selected from the group consisting of water soluble alcohols, water soluble ketones, water soluble esters, and water soluble ethers; 3) at least one monocarboxylic acid containing a primary or secondary amino group and at least one additional basic group containing nitrogen; 4) at least one metal corrosion inhibitor, the metal corrosion inhibitor being a substituted or unsubstituted benzotriazole; and 5) water. This disclosure also relates to a method of using the above composition for cleaning a semiconductor substrate.

Method of manufacturing a semiconductor device is described that uses sidewall protection of a recessed feature to prevent loss of critical dimension during a cleaning process to remove etch residue. According to one embodiment, the method includes providing a substrate containing a film thereon having a recessed feature with a sidewall and a bottom portion, depositing a conformal film on the sidewall and on the bottom portion, removing the conformal film from the bottom portion in an anisotropic etching process, where the remaining conformal film forms a protection film on the sidewall, and performing a cleaning process that removes etch residue from the recessed feature without etching the protection film or the sidewall.