Patent classifications
H01L21/02065
Semiconductor Device Package and Method of Manufacture
Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.
SUBSTRATE CLEANING ROLL, SUBSTRATE CLEANING APPARATUS, AND SUBSTRATE CLEANING METHOD
A substrate cleaning roll that has a cylindrical shape and scrubs a surface of a substrate by rotating about a rotational axis in a longitudinal direction in contact with the substrate, the longitudinal direction being parallel to the surface of the substrate, the substrate cleaning roll including a bevel cleaner at least at one end of the substrate cleaning roll in the longitudinal direction, the bevel cleaner including a sloping surface to be in contact with an outermost edge of a bevel portion at a rim of the substrate when the substrate cleaning roll comes into contact with the substrate and cleans the surface of the substrate.
METHOD OF BONDING SEMICONDUCTOR SUBSTRATES
The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.
CLEANING APPARATUS, CHEMICAL MECHANICAL POLISHING SYSTEM INCLUDING THE SAME, CLEANING METHOD AFTER CHEMICAL MECHANICAL POLISHING, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING THE SAME
A cleaning apparatus for removing particles from a substrate is provided. The cleaning apparatus includes a first cleaning unit including a first dual nozzle supplying, to a substrate, a first chemical liquid and a first spray including a first liquid dissolving the first chemical liquid, and a second cleaning unit including a second dual nozzle supplying, to the substrate, a second chemical liquid different from the first chemical liquid and a second spray including a second liquid dissolving the second chemical liquid and being the same as the first liquid.
ENGINEERED ETCHED INTERFACES FOR HIGH PERFORMANCE JUNCTIONS
Various methods for fabricating a semiconductor device by selective in-situ cleaning of a target surface of a semiconductor substrate by selective dry surface atomic layer etching of the target surface film, selectively removing one or more top layers of atoms from the target surface film of the semiconductor substrate. The selective in-situ cleaning of a target surface can be followed by deposition on the cleaned target surface such as to form a cap layer, a conductive contact layer, or a gate dielectric layer.
Method of fabricating semiconductor device
Provided are a cleaning composition for removing an organic material remaining on an organic layer and a method of forming a semiconductor device using the composition. The cleaning composition includes 0.01-5 wt %. hydroxide based on a total weight of the cleaning composition and deionized water.
METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE USING PLANARIZATION PROCESS AND CLEANING PROCESS
A method for fabricating a semiconductor structure includes following steps. First, a first layer, a second layer and a third layer are sequentially formed on the substrate. The second layer is conformally disposed on the top surface of the first layer. The second layer and the first layer have different compositions, and the third layer and the second layer also have different compositions. Then, a planarizing process is performed on the third layer until portions of the second layer are exposed. Afterwards, hydrofluoric acid and aqueous oxidant are concurrently or sequentially provided to the remaining second and third layers. Finally, an etch back process is carried out to remove all the second layer and portions of the first layer.
METHOD FOR AREA SELECTIVE DEPOSITION USING A SURFACE CLEANING PROCESS
A substrate processing method for area selective deposition. The method includes providing a substrate containing a metal film, a metal-containing liner, and a dielectric film, exposing the substrate to a plasma-excited cleaning gas containing 1) N.sub.2 gas and H.sub.2 gas, 2) N.sub.2 gas followed by H.sub.2 gas, or 3) H.sub.2 gas followed by N.sub.2 gas, forming a blocking layer on the metal film and on the metal-containing liner, and selectively depositing a material film on the dielectric film.
Composition for surface treatment and method of producing the same, surface treatment method, and method of producing semiconductor substrate
The purpose of the present invention is to provide means for sufficiently removing residues on a surface of an object which has been polished including silicon nitride, silicon oxide, or polysilicon. Provided is a composition for surface treatment including an anionic surfactant having a molecular weight of 1,000 or less and water, the composition having a pH of less than 7, wherein a ratio of a molecular weight of a hydrophilic moiety to a molecular weight of a hydrophobic moiety (the molecular weight of the hydrophilic moiety/the molecular weight of the hydrophobic moiety) of the anionic surfactant is 0.4 or more (in which the hydrophobic moiety is a hydrocarbon group having 4 or more carbon atoms and the hydrophilic moiety is a part excluding the hydrophobic moiety and a counterion), and the composition for surface treatment is used for surface treatment of an object which has been polished including at least one selected from the group consisting of silicon nitride, silicon oxide, and polysilicon.
CLEANING SOLUTION FOR REMOVING CERIUM COMPOUND, CLEANING METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR WAFER
The present invention relates to a cleaning solution for removing a cerium compound, a cleaning method, and a method for producing a semiconductor wafer. An object of the present invention is to provide a cleaning solution having excellent removability of a cerium compound. The cleaning solution for removing a cerium compound of the present invention contains an aminopolycarboxylic acid compound having a coordination number of 7 or more.