H01L21/02071

PREPARATION METHOD OF METAL CONNECTING LINE
20230055179 · 2023-02-23 ·

A preparation method of a metal connecting line includes: providing a base, where the base includes a metal conductive structure; patterned etching the base to expose a surface of the metal conductive structure; treating a surface of the base by oxygen-containing plasma to remove a charge on the surface of the metal conductive structure; and cleaning the surface of the metal conductive structure by hydrogen.

SUBSTRATE PROCESSING METHOD
20220367272 · 2022-11-17 ·

Provided is a method for processing a substrate having a metal formed on a planned dividing line along the planned dividing line, the method including a processed groove forming step of forming a processed groove in the substrate along the planned dividing line, and a burr removing step of, after the processed groove forming step is performed, making an etchant that includes at least an oxidizing agent and to which an ultrasonic vibration is imparted come into contact with the substrate, suppressing ductility of a metallic burr generated on a periphery of the formed processed groove and increasing fragility of the burr by modifying the burr by the oxidizing agent included in the etchant, and removing the burr by the ultrasonic vibration.

Transistor Gate Profile Optimization

A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
20230100606 · 2023-03-30 · ·

A method for fabricating a semiconductor device includes the steps of: forming a fin-shaped structure on a substrate, forming a gate material layer on the fin-shaped structure, performing an etching process to pattern the gate material layer for forming a gate structure and a silicon residue, performing an ashing process on the silicon residue, and then performing a cleaning process to transform the silicon residue into a polymer stop layer on a top surface and sidewalls of the fin-shaped structure.

METAL ETCHING WITH IN SITU PLASMA ASHING

An apparatus for perform metal etching and plasma ashing includes: a processing chamber having an enclosed area; an electrostatic chuck disposed in the enclosed area and configured to secure a wafer, the electrostatic chuck connected with a bias power; at least one coil connected with a source power; a etchant conduit configured provide an etchant to a metal of the wafer within the processing chamber in accordance with a photoresist mask of the wafer; and a gas intake conduit connected with a gas source, wherein the gas intake conduit is configured to supply the processing chamber with a gas from the gas source during performance of plasma ashing within the processing chamber.

CLEANING FORMULATION FOR REMOVING RESIDUES ON SURFACES

This disclosure relates to a cleaning composition that contains 1) hydroxylamine; 2) a chelating agent; 3) an alkylene glycol; and 4) water. This disclosure also relates to a method of using the above composition for cleaning a semiconductor substrate.

ABATEMENT AND STRIP PROCESS CHAMBER IN A LOAD LOCK CONFIGURATION

Examples of the present invention include a method for removing halogen-containing residues from a substrate. The method includes transferring a substrate to a substrate processing system through a first chamber volume of a load lock chamber. The load lock chamber is coupled to a transfer chamber of the substrate processing system. The substrate is etched in one or more processing chambers coupled to the transfer chamber of the substrate processing system with chemistry from a showerhead disposed over a heated substrate support assembly. The chemistry includes halogen. Halogen-containing residues are removed from the etched substrate in a second chamber volume of the load lock chamber. Cooling the etched substrate in a cooled substrate support assembly of the load lock chamber after removing the halogen-containing residue.

TREATMENT LIQUID AND METHOD FOR TREATING OBJECT TO BE TREATED
20230159864 · 2023-05-25 · ·

A treatment liquid contains water, hydroxylamine, and one or more kinds of hydrazines selected from the group consisting of hydrazine, a hydrazine salt, and a hydrazine derivative, in which a total content of the hydrazines is 1 part by mass or less with respect to 100 parts by mass of the hydroxylamine.

SELECTIVE METAL RESIDUE AND LINER CLEANSE FOR POST-SUBTRACTIVE ETCH
20230163029 · 2023-05-25 ·

Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.

Cleaning formulation for removing residues on surfaces

This disclosure relates to a cleaning composition that contains 1) hydroxylamine; 2) a chelating agent; 3) an alkylene glycol; and 4) water. This disclosure also relates to a method of using the above composition for cleaning a semiconductor substrate.